Patent
1996-02-13
1997-10-21
Donaghue, Larry D.
395391, 395392, 395384, 395382, G06F 930
Patent
active
056806370
ABSTRACT:
A RISC processor is arranged to reduce a code size, make the hardware less complicated, execute a plurality of operations for one machine cycle, and enhance the performance. The processor is capable of executing N instruction each having a short word length for indicating a single operation or an instruction having a long word length for indicating M (N<M) operations. When the number of operations to be executed in parallel is large, the long-word instruction is used. When it is small, the short-word instruction is used. A competition between the long-word instructions is detected by hardware and a competition between the short-word instructions only is detected by software. The simplification of the hardware brings about improvement of a machine cycle, improvement of a code cache hit ratio caused by the reduction of a code size and increase of the number of operations to be executed in parallel for the purpose of enhancing the performance.
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Hotta Takashi
Maejima Hideo
Nakatsuka Yasuhiro
Tanaka Shigeya
Yamada Hiromichi
Donaghue Larry D.
Hitachi , Ltd.
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