Computer graphics system with parallel processing using a switch

Details Computer graphics system with parallel processing using a switch Computer graphics system with parallel processing using a switch

1993-01-07

1995-04-18

Powell, Mark R.

395162, G06F 314

Patent

active

054086060

ABSTRACT:
Front end processors in a graphics architecture execute parallel scan conversion and shading to first process individually assigned primitive objects for providing update pixels. A crossbar accommodates data rearrangement whereby parallel pixel processors with associated memory capabilities (frame buffer banks) perform visibility and blending operations on predetermined sequences of update pixels to provide display pixels. The pixel processors identify with sequences of pixels in the display in patterns designed to equalize processor loads for pixels located along scan lines or distributed over an area. Specific distribution criteria are disclosed for patterns. One form of pixel processor organization incorporates a distributed frame buffer with FIFO memory and control stacks. Display pixels are received by a multiplexer to supply a digital-analog connector with display data in raster sequence.

REFERENCES:
patent: 4807183 (1989-02-01), Kung et al.
patent: 4918626 (1990-04-01), Watkins et al.
patent: 4949280 (1990-08-01), Littlefield
IEEE Computer Graphics and Application, Nov. 1992, "Breaking the Frame Buffer Bottleneck with Logic-Enhanced Memory", Poulton et al, pp. 65-74.
Parke, Frederic I., Simulation and Expected Performance Analysis of Multiple Processor Z-Buffer Systems, pp. 48-56, Jul. 1980, U.S. in Computer Graphics.
Stone, Harold S., High Performance Computer Architecture, pp. 305-310, 1987, U.S.
Foley, Van Dan, Feiner and Hughes, Computer Graphics: Principles and Practice, 2nd Ed., pp. 866-867, 1990, U.S.

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