Computer for synchronized read and write of vector data

Details Computer for synchronized read and write of vector data Computer for synchronized read and write of vector data

1988-07-29

1991-01-15

Zache, Raulfe B.

Boots, shoes, and leggings

3642319, 36423221, G06F 1200

Patent

active

049858270

ABSTRACT:
A computer comprising a circuit for writing a group of ordered data elements onto the main storage; a circuit for reading said group of data from the main storage; and a circuit which is connected to the writing circuit and to the reading circuit, and which ensures the sequence of main storage references between said writing circuit and said reading circuit such that said reading circuit will not read the data elements that have not yet been written by said writing circuit among said group of data elements.

REFERENCES:
patent: 4128880 (1978-12-01), Gay, Jr.
patent: 4128881 (1978-12-01), Yamamoto et al.
patent: 4302818 (1981-11-01), Niemann
patent: 4636942 (1987-01-01), Chen et al.
patent: 4780811 (1988-10-01), Aoyama et al.
patent: 4803620 (1989-02-01), Inagami et al.
Fernbach, S., "Supercomputer Class IV Systems, Hardware and Software", Elsevier Science Publishers B.V., North Holland, 1986, pp. 69-81.
Proceedings of the 12th Annual International Symposium on Computer Architecture, Jun. 17-19, 1985, Boston Mass., pp. 136-144, "MU6V: A Parallel Vector Processing System", by R. N. Ibbett, et al.

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