Computer for reducing lambda calculus expressions employing vari

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Details

3649162, 364972, 3649722, 364977, 3649771, 364973, 364DIG2, G06F 930, G06F 9302, G06F 938, G06F 1300

Patent

active

050994506

ABSTRACT:
The invention is directed to a computer including an input unit, an arithmetic logic unit, a memory unit, a control unit, an output unit, and a signal bus system connected to each of the units to permit signal communication between each of the units. The control unit of the present invention includes a problem section coupled to the memory unit, for fetching binary encoded source elements of a problem expression stored in the memory unit. In addition, the control unit includes result generator, coupled to the problem section, for generating a result expression from at least one of the source elements of the problem expression. Further, the control unit comprises a transfer unit, coupled to the result generator and the memory unit, for storing the result expression into a result area of the memory unit. The result expression comprises a plurality of address pointers to pre-identified source elements of the problem expression. The control unit further comprises a reslut section, coupled to the memory unit, for fetching the result expression from the result area of the memory unit, writing unit, coupled to the result section and the memory unit, for writing the result expression into the environment area of the memory unit; environment section, coupled to the memory unit, for fetching the result expression from the environment area of the memory unit; and comparing unit, coupled to the memory unit, for comparing at least one storage location from the result area of the memory unit with at least one storage location from the environment area of the memory unit to monitor the storage capacity of the result area and the environment area.

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