Computer for performing non-restoring division

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G06F 752

Patent

active

058187456

ABSTRACT:
A computer that performs division in either floating point or integer representation according to a novel algorithm in which a divisor is subtracted from a dividend to generate a first intermediate result. A shifter shifts the intermediate result by N-bits, where N is an integer and 2.sup.N is equal to the radix, to obtain a remainder. A look-up table produces one or more multipliers based upon an upper-bit portion of the remainder and an upper-bit portion of the divisor. The divisor is multiplied by each of the one or more multiples to generate second intermediate results. Each of the secondary intermediate results is then subtracted from the remainder to generate one or more corresponding third intermediate results. A current quotient digit is selected as the largest multiplier which corresponds to the third intermediate result having the smallest possible value (as among all of the third intermediate results).

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patent: 5638314 (1997-06-01), Yoshida
Tan, "Uniform 2 Bits Quotients Binary Division by Carry-Save Adders" IBM Technical Disclosure Bulletin vol. 14 No. 11, Apr. 1972 pp. 3279-3281.
"Computer Architecture A Quantitative Approach, Second Edition", David A. Patterson and John L. Hennessy, Morgan Kaufmann Publishers, Inc., 1996.

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