Communications: electrical – Digital comparator systems
Patent
1974-12-04
1976-06-01
Shaw, Gareth D.
Communications: electrical
Digital comparator systems
G06F 918
Patent
active
039613135
ABSTRACT:
The first time period of the instruction fetch cycle is eliminated when fetching the branch to instruction in a computer system operating in a non-overlap mode. Whenever a branch instruction is decoded, the storage address register (SAR) is directly loaded during execution of the branch instruction with certain bits from a storage data register (SDR) concatenated with certain bits from an operand register to form the branch to address in SAR. The instruction counter is incremented in the usual manner but the incremented address is not loaded into SAR. The clock is advanced to the second rather than the first time state of the next instruction fetch cycle. Thereafter, the branch to address which is residing in the operand register, is incremented and loaded into the instruction counter.
REFERENCES:
patent: 3417379 (1968-12-01), Heard et al.
patent: 3656123 (1972-04-01), Carnevale et al.
Bodner Ronald E.
Crooks Thomas L.
Magrisso Israel B.
Slack Keith M.
Smith Richard S.
Bartz C. T.
International Business Machines - Corporation
Shaw Gareth D.
Voss Donald F.
LandOfFree
Computer control apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Computer control apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Computer control apparatus will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2405471