Computer connection circuit in facsimile

Details Computer connection circuit in facsimile Computer connection circuit in facsimile

1991-11-21

1994-04-12

Coles, Sr., Edward L.

Facsimile and static presentation processing

Facsimile

Facsimile system interface

358468, 395114, H04N 132

Patent

active

053030672

ABSTRACT:
The invention provides a computer connection circuit in a facsimile, comprising: control and memory unit including CPU(Central Processing Unit)(11a), RAM(Random Access Memory)(11c), and ROM(Read Only Memory)(11b) for controlling a general operation control of the facsimile; address decoder 12 connected to the control and memory unit through an address bus, for selecting and enabling an output terminal according to an input address; a modem 31 connected to the control and memory unit through a date bus and connected to communication lines, in which is driven by a first chip selection signal of the address decoder 12 and requires an interrupt to the control and memory unit in sending/receiving image information; and an UART51(Universal Asynchronous Receiver & Transmitter) connected to the control and memory unit and to RS232C interface means of the computer, in which requites an interrupt to the control and memory unit in sending/receiving image and character information to/from the computer and is driven by a second chip selection signal of the address decoding decoder 12.

REFERENCES:
patent: 3830962 (1974-09-01), Mailoux
patent: 4613877 (1986-09-01), Spencer et al.
patent: 4652933 (1987-03-01), Koshiishi
patent: 4965676 (1990-10-01), Ejiri et al.
patent: 4991200 (1991-02-01), Lin
patent: 4996707 (1991-02-01), O'Malley, et al.
patent: 5021892 (1991-06-01), Kita et al.
Co-pending patent application Serial No. 07/778,465.
Co-pending patent application Serial No. 07/778,460.
Co-pending patent application Serial No. 07/778,459.
Western Digital Application Report #1: TR1402A Asynchronous Receiver/Transmitter, Oct. 1972.

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