Boots – shoes – and leggings
Patent
1988-05-31
1991-01-22
Zache, Raulfe B.
Boots, shoes, and leggings
3642523, G06F 1202
Patent
active
049875370
ABSTRACT:
A computer comprises an instruction memory storing therein instruction codes and including a plurality of divided address spaces, and a CPU receiving an instruction read out of the instruction memory for executing the read-out instruction and outputting an address data for an instruction code to be next executed to the instruction memory. In addition, there is provided a space code memory storing respective codes indicative of the divided address spaces within the instruction memory for respective instruction codes stored in the instruction memory, for generating an address space code for an instruction to be executed next to an instruction code designated by the address given to the instruction memory. A flipflop is provided to latch the address space code generated by the space code memory so as to supply the latched address space code to the instruction memory after one instruction execution time, so that the instruction memory is address-designated by a combination of the address data outputted from the CPU and the address space code delayed by the flipflop.
REFERENCES:
patent: 4340932 (1982-07-01), Bakula et al.
patent: 4485457 (1984-11-01), Balaska et al.
patent: 4500961 (1985-02-01), Engles
patent: 4592011 (1986-05-01), Mantellina et al.
patent: 4831522 (1989-05-01), Henderson et al.
NEC Corporation
Zache Raulfe B.
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