Computer bus utilization determination apparatus

Details Computer bus utilization determination apparatus Computer bus utilization determination apparatus

1995-11-08

1997-11-18

Heckler, Thomas M.

395287, G06F 1314

Patent

active

056896913

ABSTRACT:
Circuitry for monitoring the idle periods on the EISA bus and a program using this known value to determine percentage utilization of the EISA bus. A counter is used to count the number of synchronizing clock periods during which the EISA bus is idle. To determine if the EISA bus is idle, certain logic monitors the EISA bus signals and the arbiter activity to determine if cycles are actually occurring. If so, the EISA bus is not idle and the counter is not incremented. If there is no activity, the counter increments on each BCLK clock. The computer system periodically reads this counter. The computer system determines the interval between read operations of the counter and uses this interval in combination with the counter value and BCLK signal rate to determine the percentage utilization.

REFERENCES:
patent: 4719567 (1988-01-01), Whittington et al.
patent: 5241632 (1993-08-01), O'Connell et al.
patent: 5263163 (1993-11-01), Holt et al.

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