Patent
1996-05-21
1998-04-07
Harvey, Jack B.
395308, 395306, 395309, 395287, 395290, 395293, 395281, 395822, 395842, 395847, 395728, 395733, H01J 1300
Patent
active
057375453
ABSTRACT:
A method and system are designed to guarantee availability of ownership of an ISA bus by a bus mastering or a direct memory access device in a system also including a PCI bus. This is accomplished by placing a lock on the PCI bus through a bridge device to a configuration read of a PCI configuration space register. Once the lock is established, other PCI devices are prevented from locking any other resource on the PCI bus. The PCI configuration space exists outside of the memory or I/O ranges to which an ISA resident device can generate access. Consequently, whenever the ISA resident device generates its access, it is to a device known not to be in a locked state. Consequently, the bus transaction is capable of completion within the time limit expected by the ISA resident device.
REFERENCES:
patent: 5467295 (1995-11-01), Young et al.
patent: 5506995 (1996-04-01), Yoshinoto et al.
patent: 5555381 (1996-09-01), Ludwig et al.
patent: 5557758 (1996-09-01), Bland et al.
patent: 5572734 (1996-11-01), Narad et al.
Davis Barry Martin
Demers Richard
Fall Brian Neil
Wszolek Philip
Harvey Jack B.
Phan Raymond N.
Ptak LaValle D.
VLSI Technology Inc.
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