Computer bus deadlock prevention

Details Computer bus deadlock prevention Computer bus deadlock prevention

1986-11-25

1989-09-19

Kemeny, Emanuel S.

Boots, shoes, and leggings

G06F 1516, G06F 1336

Patent

active

048687413

ABSTRACT:
A digital computing system includes at least a first and a second bus with at least a first master connected to the first bus and a second master connected to the second bus. The first master is capable of requesting the second bus through the first bus and the second master is capable of requesting the first bus through the second bus. Central conversion means receives both requests and has circuitry for generating a response signal to the first bus when both requests come simultaneously. The first master receives the response signal and continues the cycle, but without continuing the request for the second bus. The cycle is completed as though the request had been completed.

REFERENCES:
patent: 4035777 (1977-07-01), Moreton
patent: 4228496 (1980-10-01), Katzman et al.
patent: 4234919 (1980-11-01), Bruce et al.
patent: 4257099 (1981-03-01), Appelt
patent: 4363094 (1982-12-01), Kurl et al.
patent: 4484273 (1984-11-01), Stiffler et al.
patent: 4494193 (1985-01-01), Brahm et al.
patent: 4495571 (1985-01-01), Staplin, Jr. et al.

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