Computer bus arbitration for N processors requiring only N unidi

Details Computer bus arbitration for N processors requiring only N unidi Computer bus arbitration for N processors requiring only N unidi

1992-06-25

1994-05-17

Fleming, Michael R.

Boots, shoes, and leggings

36424292, 364DIG1, 36493701, 364DIG2, G06F 13368

Patent

active

053135911

ABSTRACT:
A system and method for using N unidirectional lines to implement signals for arbitration, variable length transactions, automatic responses, and efficient burst transaction modes for a bus in a cache-coherent multi-processor computer system having N processors. Processors use arbitration lines to implement busy signals for variable length transactions. A processor needing to respond to a transaction is granted automatic access to a bus if it is the last processor asserting a busy signal. A processor in a burst transaction mode is granted automatic continuous access without arbitration if no other processors request access. The use of only N lines minimizes pin-out for an integrated processor. The use of unidirectional (one driver, N-1 receivers) lines further optimizes cost and speed.

REFERENCES:
patent: 4920486 (1990-04-01), Nielsen
patent: 5191649 (1993-03-01), Cadambi et al.
patent: 5195185 (1993-03-01), Marenin

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