Patent
1997-06-30
1999-04-06
An, Meng-Ai T.
39580001, 39580028, 39580029, 39580032, 395821, 395828, 395859, 395872, 395882, 395892, G06F 1300
Patent
active
058929649
ABSTRACT:
A core logic chip set is provided in a computer system to provide a bridge between host and memory buses and an accelerated graphics port ("AGP") bus adapted for operation of two AGP devices, or one AGP device and one peripheral component interconnect ("PCI") device. A common AGP bus having provisions for the PCI and AGP interface signals is connected to the core logic chip set and the AGP and/or PCI device(s). The core logic chip set has an AGP/PCI arbiter having Request ("REQ") and Grant ("GNT") signal lines for each AGP and/or PCI device connected to the AGP bus. Another embodiment has a plurality of AGP buses for a plurality of AGP devices. This allows concurrent operation for AGP devices connected to different AGP buses. Two of the AGP buses may be combined to connect to one 64 bit PCI device.
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Horan Ronald Timothy
Olarig Sompong
Thome Gary W.
An Meng-Ai T.
Chichester Ronald L.
Compaq Computer Corp.
Katz Paul N.
Nguyen Dzung
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