Computer automated method for manufacturing an integrated...

Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle – Manufacturing optimizations

Reexamination Certificate

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C716S050000, C716S051000, C716S052000, C716S053000, C716S055000, C430S005000, C430S030000

Reexamination Certificate

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07958463

ABSTRACT:
A computer automated method for designing an integrated circuit includes placing a plurality of marks on each of contours of a plurality of patterns allocated in a chip area; dividing the marks into a plurality of groups so that the adjacent marks are merged in a same group; determining one of the groups as a candidate hot spot based on a total number of marks included in each of the groups; and modifying the corresponding pattern in the candidate hot spot.

REFERENCES:
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patent: 6631307 (2003-10-01), Tzu et al.
patent: 6668367 (2003-12-01), Cobb et al.
patent: 6952818 (2005-10-01), Ikeuchi
patent: 7194707 (2007-03-01), Kotani et al.
patent: 08-137087 (1996-05-01), None
patent: 2000-187314 (2000-07-01), None
patent: 2003-162041 (2003-06-01), None
patent: 2003-257842 (2003-09-01), None
patent: 2004-302110 (2004-10-01), None
Official Office Action Letter issued on Feb. 10, 2009, in Taiwan application No. 094137590, including Japanese language translation thereof.

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