Computer assisted method for partitioning an electric circuit

Data processing: structural design – modeling – simulation – and em – Modeling by mathematical expression

Reexamination Certificate

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C716S030000

Reexamination Certificate

active

07047162

ABSTRACT:
A partition of an electrical circuit is formed in that the electrical circuit is imaged on a graph (102) and weighting values are allocated (103) to the edges of the graph. The weighting values describe a required calculating outlay for determining electrical descriptive quantities for the respective element of the electrical circuit represented by the edge. A check is carried in iterative methods to see whether, proceeding from preceding iteration steps, a sum of the weighting values of edges grouped together lies between a first threshold and a second threshold by adding a further edge. When this is the case, then a further check is carried out to see whether a plurality of terminals of the elements within the partition to elements outside the partition is increased by adding new edges. When this is not the case, then the respective edge is also incorporated into the partition.

REFERENCES:
patent: 5587922 (1996-12-01), Hendrickson et al.
patent: 5748844 (1998-05-01), Marks
patent: 5761077 (1998-06-01), Shackleford
patent: 5805459 (1998-09-01), Kapoor
patent: 6031979 (2000-02-01), Hachiya
patent: 6212668 (2001-04-01), Tse et al.
Kapp et al., “Improved Cost Function for Static Partitioning of Parallel Circuit Simulations Using Conservative Sychronization Protocol”, Proceedings Ninth Workshop on Parallel and Distributed Simulation, pp. 78-85, Jun. 1995.
Peinado et al., “Parallel Go With the Winners' Algorithms in the LogP Model”, Proceedings International Parallel Processing Symposium, pp. 656-664, Apr. 1997.
Buch et al., “A Parallel Graph Partitioner on a Distributed Memory Processor”, Proceedings Fifth Symposium on Frontiers of Massively Parallel Computation, pp. 360-366, Feb. 1995.
Talbi et al., E.-G. A Parallel Genetic Algorithm for the Graph Partitioning Problem, Proceedings of the 5th International Conference on Supercomputing, Jun. 1991, pp. 312-320.
U. Kleis, et al.,Domain Decomposition Methods for Circuit Simulation,Proceedings of the 8thWorkshop on Parallel and Distributed Simulation, PADS, Edinburgh, UK (Jul., 1994), pp. 183-186.
U. Wever, et al.Parallel Transient Analysis for Circuit Simulation,Proceedings of the 29thAnnual Hawaii International Conference on System Sciences (1946), pp. 442-447.
B. Riess, et al.,Partitioning Very Large Circuits Using Analytical Placement Techniques,Proceedings of the 31stACM/IEEE Design Automation Conference (1994), pp. 646-51.
P. Johannes,Partitioning of VLSI Circuits and Systems,33rdDesign and Automation Conference, Las Vegas (Jun. 3-7, 1996), pp. 83-87.
J. Cong, et al.,A Parallel Bottom-up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design,In: 30thDesign Automation Conference, Jun. 14-18, 1993, pp. 755-760.
J. Li, et al.,New Spectral Linear Placement and Clustering Approach,33rdDesign Automation Conference, Las Vegas (Jun. 3-7, 1996), pp. 88-93.
T. Kage, et al.,A Circuit Partitioning Approach for Parallel Circuit Simulation,IEICE Trans Fundamentals, vol. E77-A, No. 31 (1993), pp. 461-465.
G. Hung, et al.,Improving the Performance of Parallel Relaxation-Based Circuit Simulators,IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, New York (Nov. 12, 1993), No. 11, pp. 1762-1774.

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