Computer assisted fault isolation in circuit board testing

Details Computer assisted fault isolation in circuit board testing Computer assisted fault isolation in circuit board testing

1985-07-29

1987-11-24

Smith, Jerry

Excavating

371 25, 371 26, 371 29, 324 73R, G01R 3128

Patent

active

047093668

ABSTRACT:
Circuit faults in an electronic system are isolated by a programmed computer that guides a technician node-by-node on a unit under test (UUT), such as a circuit board, to the source of a failure. Stimulus pattern signals are applied to the circuit, and responses at the circuit nodes are made by a measurement probe under the hand of the technician. As each node is probed, a stimulus pattern signal tailored for testing that node is applied to the UUT. The measured response is compared to a predetermined response corresponding to an operational UUT to generate a failure accusation or recommend the next node to be probed. The computer is programmed to expedite the search for the source of the failure by displaying to the technician clues which define the circuit nodes most apt to be defective as a result of preliminary functional testing of the UUT. The computer is further programmed to have a form of "intuition" whereby the particular nodes recommended for probing are determined in part by prior testing of the same type of UUT.

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W. E. Forster, "Guaranteed On-Line Diagnoses", IBM Tech. Bulletin, vol. 21, No. 11, 4/1979, pp. 4433-4437.
"Real-Time Mapping of a Memory Storage . . . ", IBM Tech. Bulletin, vol. 28, No. 4, 9/1985, p. 1567.

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