Computer architecture with caching of history counters for...

Details Computer architecture with caching of history counters for... Computer architecture with caching of history counters for...

2005-01-04

2005-01-04

Barot, Bharat (Department: 2155)

Electrical computers and digital processing systems: multicomput

Multicomputer data transferring via shared memory

C709S214000, C711S148000

Reexamination Certificate

active

06839739

ABSTRACT:
A multi-processor system using distributed memory is provided with a cache of history counters located within each memory controller. Each entry of the cache of history counters represents one page in memory that has the potential to increase system performance by migrating or replicating to other memory locations. The cache of history counters permits creating histories of local memory accesses by remote processors for purposes of dynamic page placement.

REFERENCES:
patent: 5297265 (1994-03-01), Frank et al.
patent: 5727150 (1998-03-01), Laudon et al.
patent: 5734922 (1998-03-01), Hagersten et al.
patent: 5784697 (1998-07-01), Funk et al.
patent: 5893144 (1999-04-01), Wood et al.
patent: 5918249 (1999-06-01), Cox et al.
patent: 5974536 (1999-10-01), Richardson
patent: 6035378 (2000-03-01), James
patent: 6167437 (2000-12-01), Stevens et al.
patent: 6332178 (2001-12-01), Dean et al.

Affiliated with

Also associated with

Rating

Computer architecture with caching of history counters for... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Computer architecture with caching of history counters for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Computer architecture with caching of history counters for... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3419615