Boots – shoes – and leggings
Patent
1988-12-02
1995-10-17
Harrell, Robert B.
Boots, shoes, and leggings
364DIG1, 364DIG2, 395375, 395494, G06F 1200
Patent
active
054598460
ABSTRACT:
A computer system having an improved memory architecture uses a variety of memory speed enhancement features that can be used in combination. For example, the memory is scanned out across memory blocks, unnecessary row addressing operations are detected and eliminated, and the memory is organized to reduce row addressing operations for combinations of instruction accesses interspersed by operand accesses. In a DRAM configuration, unnecessary CAS addressing cycles and RAS addressing cycles are detected and eliminated. A memory address detector circuit in the memory controller determines the nature of the memory cycle; chip select, RAS, or CAS; needed to access stored digital information and deletes unnecessary cycles.
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Harrell Robert B.
Hyatt Gilbert P.
Roth Gregory L.
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