Computer architecture for reducing delays due to branch instruct

Boots – shoes – and leggings

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

395587, 395588, 364247, 3642473, 3642476, 3642477, 364DIG1, G06F 938

Patent

active

056153864

ABSTRACT:
An improved data processing system for executing branch instructions which has lower latency times and which only rarely requires the instruction pipeline to be flushed is disclosed. The data processing system utilizes a register file to hold the information needed to execute a branch instruction. The information is loaded into the register file in advance of the branch instruction. This allows the system to prepare more than one branch instruction at any given time. The present invention may be used to cause the cache line containing the target address of the branch instruction to be loaded soon as the target address is available for the branch instruction. Since the outcome of the branch instruction is almost always known when the branch instruction enters the instruction pipeline, the instruction pipeline only rarely needs to be flushed.

REFERENCES:
patent: 4334268 (1982-06-01), Boney et al.
patent: 4435758 (1984-03-01), Lorie et al.
patent: 4742466 (1988-03-01), Ochiai et al.
patent: 4755935 (1988-07-01), Davis et al.
patent: 4764861 (1988-08-01), Shibuya
patent: 4933847 (1990-06-01), Chau et al.
patent: 5050068 (1991-09-01), Dollas et al.
patent: 5134701 (1992-07-01), Mueller et al.
patent: 5193156 (1993-03-01), Yoshida et al.
patent: 5197136 (1993-03-01), Kimura et al.
"Reducing the Cost of Branches by Using Registers" by Jack W. Davidson and David B. Whalley, Department of Computer Science, University of Virginia, 1990 IEEE.
Hewlett Packard, "PA-RISC 1.1, Architecture and Instruction Set," Reference Manual, Nov. 1990.
Lilja "Reducing the branch penalty in pipelined processor", IEEE Jul. 1988, pp. 47-54.
Farrens "Overview of the pipe processor implementation.", IEEE 1991, 433-443.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Computer architecture for reducing delays due to branch instruct does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Computer architecture for reducing delays due to branch instruct, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Computer architecture for reducing delays due to branch instruct will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2212402

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.