Computer aided design system capable of placing functional block

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364489, G06F 1520

Patent

active

051649071

ABSTRACT:
A system and method for logic circuit design in which functional blocks are placed on a substantially plane area in compliance with logic connection information under a circuit constraint. Critical nets are first extracted from logic connection information and then, critical blocks connected to the critical nets are extracted from the logic connection information. The critical blocks are initially placed on the substantially plane area to provide an initial critical block placement result. The initial critical block placement result is iteratively improved until the circuit constraint is satisfied.

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Robson, Gary, "Automatic Placement and Routing of Gate Arrays", VLSI Design, Apr., 1984, pp. 35-36, 38-40, and 42-43.

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