Computer-aided design methods and apparatus for multilevel inter

Details Computer-aided design methods and apparatus for multilevel inter Computer-aided design methods and apparatus for multilevel inter

1995-09-25

1997-03-11

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364490, 364578, G06F 1750

Patent

active

056108338

ABSTRACT:
Data processing methods and computer display systems for computer aided design and electrical performance prediction of multilevel on-chip and off-chip interconnects. The invention specifically relates to parameterized graphical display and computation tools for calculation and display of capacitance and other electrical characteristics of multilevel VLSI, PCB, and MCM interconnects. Four subsystems are integrated: (a) a batch-mode computation module that combines a 2-D/3-D finite difference numerical simulation and a fast interpolation algorithm; (b) an interactive design mode with performance browsing, goal-directed synthesis, and on-line performance evaluation; (c) an interactive SPICE subcircuit generator and simulator; and (d) a spreadsheet-style graphical user interface.

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