Computer address modification system with optional DMA paging

Details Computer address modification system with optional DMA paging Computer address modification system with optional DMA paging

1987-08-10

1989-07-18

Williams, Jr., Archie E.

Boots, shoes, and leggings

3642423, 364255, 36424231, G06F 936, G06F 1300, G06F 1328

Patent

active

048498750

ABSTRACT:
A computer system includes a computer address modification system that is advantageously coupled in a bus network to selectively translate memory address data in 16K blocks and provide DMA page addresses in 16K blocks which may match the 16K memory address blocks. The modification system includes a mapping RAM selectively providing translated addresses to enable addresses in a 16 megabyte extended address space. The modification system also includes a page register storing for each addressable 16K block of data for each DMA channel a page address within the extended address space.

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Technical Reference Manual--IBM PC AT, Version 1.0, Mar. 1984, Sections I-VI.
Victor VI Memory Mapper System Interface Description, NNA Corporation, 1985, Section VI.
Expanded Memory Device Specification (3.0), Intel.
IBM Technical Disclosure Bulletin, vol. 25, No. 7B, Dec. 1982, p. 3865.

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