Electrical computers and digital processing systems: processing – Processing architecture – Data driven or demand driven processor
Reexamination Certificate
1998-08-05
2001-06-05
Eng, David Y. (Department: 2155)
Electrical computers and digital processing systems: processing
Processing architecture
Data driven or demand driven processor
C712S018000, C712S032000, C712S201000, C712S202000
Reexamination Certificate
active
06243800
ABSTRACT:
This application claims priority of Russian Federation application 97113129 filed Aug. 6, 1997.
INTRODUCTION
The invention relates to computer science and, in particular, to computing devices that use dataflow control for information processing especially for use in high performance digital computing systems.
BACKGROUND OF THE INVENTION
An information processing device using dataflow for information processing has been disclosed by Uchida in U.S. Pat. No. 4,675,806. Uchida describes a system in which instruction processing is performed on the basis of the availability of data and in which the flow of data and instructions are separated but the data is transferred as directed and required by the instructions. This device has a relatively low level of performance which is common to other computing devices which use dataflow control over computation and direct addressing operative memory as the hardware means for data storage. The reduced performance is due to the complicated hardware organization of the control means and to the expenditure of time during the process of the dynamic distribution of memory.
Another known data processing device, described in Russian Federation Patent 2029359, which uses dataflow for control of the computation process, contains a processor, an input-output switch, instruction loading switch, instruction memory, data access unit, and first and second information outputs. In this device, the first control output of the processor is connected with the first control input of the input-output switch, the first control input of which is connected with the first control input of the data access unit, the first information input of which is connected with the information output of the instruction loading switch, the first control input of which is connected with the second control output of the processor, the first and second information outputs of which are connected correspondingly with the first information input of the instruction loading switch and the first information input of the input-output switch, the third information output of the processor is connected with the first information output of the computer, the zeroizing input of the data access unit is connected to the zeroizing output of the computer, and the information input of instruction memory and the information input of the instruction loading switch are connected with the first information input of the computer.
This device uses dataflow for control of the computation process and associative memory (data access unit) hardware for storage of data and results. The associative memory simultaneously performs the function of control means hardware. Accordingly, since there is no loss of time on the processes of memory distribution, performance increases.
However, in this device, the performance of the device depends directly on the associative memory (in data access unit) and is defined by the speed of data output from associative memory (number of operands ready to performance in a unit of time N=1/Tam, where Tam=time of work of associative memory from the moment of inquiry to the output of data).
The value Tam depends directly on the volume of associative memory. Since Tam, measured from the time of inquiry from a running routine, increases as the size of the associative memory increases, the performance of the device decreases as the size of the associative memory increases.
Thus, the device fails to achieve a high level of performance when large volumes of running routines are processed.
SUMMARY OF THE INVENTION
It is an object of the invention to increase performance by decreasing the volume of associative memory while at the same time introducing the local use of data processing according to von Neumann principals of computation without violating the common idea of dataflow control of computation.
It is an object of the invention to improve performance by introducing a fragment routine processing unit into a dataflow processing system whereby fragment routines, which are routines which are better suited to processing by the von Neumann principle of computation, are directed to the fragment routine processing unit for processing.
This is achieved in the computer containing processor, input-output switch, instruction loading switch, instruction memory, data access unit, first and second information output, zeroizing input, and first and second information inputs. The first control output of the processor is connected with the first control input of the input-output switch. The first control output of the input-output switch is connected with the first control input of the data access unit. The first information input of the data access unit is connected with the information output of the input-output switch. The address input of instruction memory is connected with the information output of the instruction loading switch. The first control input of the instruction loading switch is connected with the second control output of the processor. The first and second information outputs of the processor are connected respectively with the first information input of the instruction loading switch and the first information input of the input-output switch. The third information output of the processor is connected with the first information output of the computer. The zeroizing input of the data access unit is connected with the zeroizing input of the computer. The information input of instruction memory and the second information input of the instruction loading switch are connected with the first information input of the computer. The fragment routine processing unit is introduced. The first control output of the fragment routine processing unit is connected with the second control input of the data access unit. The first control output of the data access unit is connected with the second control input of input-output switch. The second control output of the input-output switch is connected with the first control input of the processor and the first control input of the fragment routine processing unit. The second control output of the fragment routine processing unit is connected with the third control input of the input-output switch. The second information input of the input-output switch is connected with the information output of the fragment routine processing unit. The second control output of the data access unit is connected with the second control input of the processor. The first information input of the processor is connected with the information output of instruction memory. The control input of instruction memory is connected with the control output of the instruction loading switch. The second control input of the instruction loading switch and the first information input of the fragment routine processing unit are connected with the first information input of the computer. The control output of instruction memory is connected with the third control input of the processor. The third control output of the processor is connected with the third control input of the data access unit. The second information input of the data access unit is connected with the second information input of the computer. The zeroizing input of the computer is connected with the second control input of the fragment routine processing unit, with the fourth control input of the data access unit, with the fourth control input of the input-output switch and with the fourth control input of the processor. The fourth control output of the processor is connected with the fifth control input of the data access unit. The third information input of the data access unit is connected with the second information output of the processor. The fifth control input of the processor is connected with the third control output of the data access unit. The first information output of the data access unit is connected with the second information input of the processor. The second information output of the data access unit is connected with the second information output of the computer. The third control input of the f
Burtsev Vsevolod Sergeevich
Erschov Vladimir K.
Fyodorov Vjachoslav B.
Khailov Igor K.
Koslov Lev A.
Costa John G.
Eng David Y.
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