Computational nodes and computational-node networks that...

Details Computational nodes and computational-node networks that... Computational nodes and computational-node networks that...

2011-06-07

2011-06-07

Sparks, Donald (Department: 2129)

Data processing: artificial intelligence

Neural network

Structure

Reexamination Certificate

active

07958071

ABSTRACT:
Embodiments of the present invention are employ dynamical, nanoscale devices, including memristive connections between nanowires, for constructing parallel, distributed, dynamical computational networks and systems, including perceptron networks and neural networks. In many embodiments of the present invention, neuron-like computational devices are constructed from silicon-based microscale and/or submicroscale components, and interconnected with one another by dynamical interconnections comprising nanowires and memristive connections between nanowires. In many massively parallel, distributed, dynamical computing systems, including the human brain, there may be a far greater number of interconnections than neuron-like computational nodes. Use of dynamical nanoscale devices for these connections results in enormous design, space, energy, and computational efficiencies.

REFERENCES:
patent: 5179631 (1993-01-01), Guddanti et al.
patent: 5706404 (1998-01-01), Colak
patent: 6889216 (2005-05-01), Nugent
patent: 2006/0266999 (2006-11-01), Snider et al.
patent: 2007/0005532 (2007-01-01), Nugent
Chua, L.O. et al. “Autonomous Cellular Neural Networks: A Unified Paradigm for Pattern Formation and Active Wave Propagation”, IEEE Trans. on Circuits and Systems-I: Fundamental Theory and Applications, vol. 42, No. 10, Oct. 1995, pp. 559-577.
Chua, L.O. “Nonlinear Circuit Foundations for Nanodevices, Part I: The Four-Element Torus”, Proc. Of the IEEE, vol. 91, No. 11, Nov. 2003, pp. 1830-1859.
Morie, T. et al. “A 1-D CMOS PWM Cellular Neural Network Circuit and Resistive-Fuse Network Operation”, in: Ext. Abs. of Int. Conf. on Solid State Devices and Materials, the Japan Society of Applied Physics, 2001, pp. 90-91.
Nakano, T. et al. “Coarse image region segmentation using resistive-fuse networks implemented in FPGA”, Proc. The 7th World Multiconference on Systemics, Cybernetics and Informatics (SCI 2003), vol. 4, 2003, pp. 186-191.

Affiliated with

Also associated with

Rating

Computational nodes and computational-node networks that... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Computational nodes and computational-node networks that..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Computational nodes and computational-node networks that... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2678496