Computational method and apparatus for finite field multiplicati

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364746, G06F 752, G06F 738

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047455683

ABSTRACT:
A multiplier for obtaining the product of two elements in the field GF(2.sup.m) utilises the normal basis representation of each element. The product is also represented in normal basis form with each binary digit of the bit vector being determined by a sum of the product of the binary digits representing the two elements. By grouping like ones of one of the binary digits in the expression for the binary digit of the product and offsetting the suffixes of the binary digits, it is possible to accumulate grouped terms of each of the binary digits of the product simultaneously.

REFERENCES:
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patent: 4251875 (1981-02-01), Marver et al.
patent: 4587627 (1986-05-01), Omura et al.
C. C. Wang et al., "VLSI Architectures for Computing Multiplications and Inverses in GF (2.sup.m), IEEE Trans. on Computers, vol. C-34, No. 8, Aug. 1985, pp. 709-717.
B. A. Laws, Jr. et al., "A Cellular-Array Multiplier for GF (2.sup.m)", IEEE Trans. on Computers, vol. C-20, No. 12, Dec. 1971, pp. 1573-1578.
K. Z. Pekmestzi et al., "A Two's Complement Cellular Array Multiplier", The Radio and Electronic Engineer, vol. 51, No. 2, Feb. 1981, pp. 94-96.

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