Computational circuit

Details Computational circuit Computational circuit

1999-12-14

2001-03-13

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific input to output function

Exponential

C327S355000, C327S361000

Reexamination Certificate

active

06201430

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a computational circuit, and more specifically, to a squaring circuit using a MOS or MIS transistor.
Hitherto, MOS transistors are exclusively employed in digital circuits using digital signals “0” and “1”. On the other hand, recently, it has been increasingly desired for the MOS transistor to handle analog signals. For example, a squaring circuit is required for a full wave rectification of a small alternating-current signal. In this case, if the signal is digitally processed, it is necessary to employ an AD converter circuit, a digital squaring circuit, and a DA converter circuit, which result in increases of a chip size and a manufacturing cost.
On the other hand, the MOS transistor is characterized in that a drain current having a component in proportion to square of an input voltage between a gate and a source is output. Assuming that the voltage between the gate and the source is represented by Vgs and a threshold voltage is represented by Vth, the drain current Id is given by the following equation:
Id=K(Vgs−Vth)
2
  (1)
where K is a constant in relation to a gate length and width (see “Ultrafast MOS device edited by Koyama Shin, Baifu kan, Tokyo, page 8).
However, as is apparent from the equation (1), the output current Id includes a component associated with the threshold voltage Vth. Therefore, the output current is largely distorted.
In the method in which a squared alternating-current signal is obtained by using the formula (1), an element associated with the threshold voltage is included. As a result, only a signal largely distorted is obtained.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to provide a MOS or MIS computational circuit for obtaining a squared alternating-current signal without distortion.
To attain the aforementioned object, the computational circuit according to a first aspect of the present invention comprises:
a first MIS transistor having a gate to which a first input signal is applied;
a second MIS transistor having a gate to which a second input signal is applied and having substantially the same current driving ability as that of the first MIS transistor;
a third MIS transistor having a gate to which a signal obtained by adding the first input signal and the second input signal is applied; and
an adding-subtracting circuit for adding a drain current of the first MIS transistor and a drain current of the second MIS transistor to obtain an addition result, subtracting a current corresponding to a substantially two-fold drain current of that of the first MIS transistor from the addition result on the basis of a drain current of the third MIS transistor, and outputting a subtraction result,
wherein when a signal obtained by superimposing a first AC signal to a first DC voltage is supplied as the first input signal, and a signal obtained by superimposing a second AC signal having the same absolute value peak voltage as the first AC signal and a reversed phase of the first AC signal to a second DC voltage having the approximately same voltage as the first DC voltage is supplied as the second input signal, a squared signal of the first AC signal of the first input signal is output as the subtracting result from the adding-subtracting circuit.
A computational circuit according to a second aspect of the present invention comprising:
a first MIS transistor having a gate to which a first input signal is applied, and having a channel of a first conductivity type;
a second MIS transistor having a gate to which a second input signal is applied, having a channel of the first conductivity type and having substantially the same current driving ability as that of the first MIS transistor;
a third MIS transistor having a gate to which a signal obtained by adding the first input signal to the second input signal is applied, and having a channel of the first conductivity type;
an adding-subtracting circuit for adding a first drain current of the first MIS transistor and a second drain current of the second MIS transistor to obtain an addition result, subtracting a current corresponding to a substantially tow-fold drain current of that of the first MIS transistor from the addition result, based on a third drain current of the third MIS transistor, and outputting a subtraction result; and
an output terminal to which the subtraction result of the adding-subtracting circuit is output,
wherein each source of the first, the second and the third MIS transistors is connected to a first power supply potential and the adding-subtracting circuit includes fourth and fifth MIS transistors each having a channel of a second conductivity type, and each source of the fourth and the fifth MIS transistor is connected to a second power supply potential, gates of the fourth and the fifth MIS transistors are connected in common to a drain of the fifth MIS transistor, the drain of the fifth MIS transistor is connected to a drain of the third MIS transistors, and a drain of the fourth MIS transistor is connected to drains of the first and the second MIS transistors and the output terminal.
In the present invention, an alternating-current signal having a frequency component is input to the first MIS transistor gate. A signal identical in frequency to signal input to the first MIS transistor but reversal in phase is input to the second MIS transistor. Furthermore, a direct-current component input to the first and second MIS transistors is input to the third MIS transistor. It is therefore possible to obtain a squared signal of the alternating-current component by subtracting a direct current which is twice the drain current of the first or second MIS transistor on the basis of the drain current of the third MIS transistor from the drain currents of the first and second MIS transistors. Therefore, squared alternating current component less in distortion and independent of a threshold of a transistor can be obtained.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.


REFERENCES:
patent: 4047059 (1977-09-01), Rosenthal
patent: 5581211 (1996-12-01), Kimura
patent: 5617053 (1997-04-01), Shou et al.
patent: 5783954 (1998-07-01), Kholfman et al.
patent: 6107858 (2000-08-01), Kimura

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