Patent
1996-03-04
1998-05-12
Heckler, Thomas M.
G06F 104
Patent
active
057520127
ABSTRACT:
A computational array includes a self timed computational element that performs self timed calculations internally independent of a global clock. The self timed computational element includes a computational unit (100) which produces a complete signal upon the completion of calculation of a result value. The self timed computational element also includes a self timed control unit (200) which determines whether a new result value is to be calculated by the computational unit (100) based on an iteration signal which indicates a number of times the new result value is to be calculated, and based on the complete signal received from the computational unit (100) indicating that each previous calculation has been completed. Upon determining that a new result value is to be calculated, the self timed control unit (200) provides a self timed clock signal to the computational unit (100) and the computational unit (100) calculates the new result value accordingly.
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patent: 5450557 (1995-09-01), Kepp et al.
patent: 5487153 (1996-01-01), Hammerstrom et al.
"A Fully Asynchronous Digital Signal Processor Using Self-Timed Circuits", Gordon M. Jacobs and Robert W. Brodersen, IEEE Journal of Solid-State Circuits, vol. 25, No. 6, Dec. 1990, pp. 1526-1537.
Heckler Thomas M.
Motorola
Pickens S. Kevin
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