Computational array circuit for providing parallel multiplicatio

Details Computational array circuit for providing parallel multiplicatio Computational array circuit for providing parallel multiplicatio

1995-03-03

1997-03-04

Malzahn, David H.

Boots, shoes, and leggings

364735, 3647505, G06F 1711

Patent

active

056086636

ABSTRACT:
A computational array circuit (100) performs parallel multiplications with an adder array (140). The computational array circuit converts a floating point input value to a logarithmic input value. The logarithmic input value is then added to a logarithm of a multiplier value by an adder circuit (145) in each of a number of array elements (150) of the adder array (140). The computational array circuit (100) converts the resulting logarithmic output value from each of the array elements (150) to an antilogarithmic output value. The antilogarithmic output value from each of the array elements is thus the mathematical equivalent of the floating point input value multiplied by the multiplier value. The computational array circuit (100) thus obtains the advantage of floating point precision and range while requiring far less physical area than floating point multipliers would require to perform the same functions.

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patent: 4720809 (1988-01-01), Taylor
patent: 5060181 (1991-10-01), Matsuoka
"A 10-ns Hybrid Number System Data Execution", Fang-shi Lai, IEEE Journal Of Solid-State Circuits, vol. 26, No. 4, Apr. 1991.
"A Hybrid Number System Processor With Geometric And Complex Arithmetic Capabilities", Fang-shi Lai and Ching-Farn Eric Wu, IEEE Transactions On Computers, vol. 40, No. 8, Aug. 1991.
"The Efficient Implementation And Analysis Of A Hybrid Number System Processor", Fang-shi Lai, IEEE Transactions On Circuits And Systems--II: Analog And Digital Signal Processing, vol. 40, No. 6, Jun. 1993.

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