Computation circuit having dynamic range extension function

Details Computation circuit having dynamic range extension function Computation circuit having dynamic range extension function

2006-08-08

2006-08-08

Malzahn, D. H. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

07089277

ABSTRACT:
A computation circuit which can obtain n+m-digit accumulation results by using an n-digit computation unit. This computation circuit comprises a computation unit which performs additions of n-digit data; an m-digit up/down counter; and a control circuit which uses the up/down counter to generate the upper m digits of the computation result. In a preferred embodiment, the control circuit increments by one the up/down counter when carry-over occurs in the computation unit, and when the input data of the computation unit is negative, decrements by one the up/down counter. In another preferred embodiment, the control circuit increments or decrements by one the up/down counter when positive or negative overflow occurs in the computation unit, and decrements by one the up/down counter when the final computation result of the computation unit is negative or is a positive number greater than 2n−1−1.

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patent: 5319588 (1994-06-01), Haines et al.
patent: 6243731 (2001-06-01), Tessarolo
patent: 7013321 (2006-03-01), Saulsbury
patent: 2000-35875 (2000-02-01), None

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