Compressive bump-and-socket interconnection scheme for integrate

Details Compressive bump-and-socket interconnection scheme for integrate Compressive bump-and-socket interconnection scheme for integrate

1993-04-13

1994-07-12

Picard, Leo P.

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

361762, 361767, 361792, 361808, 257692, 257738, 439 66, 174 524, 174263, H05K 702

Patent

active

053294238

ABSTRACT:
A electrically interconnected assembly includes an electronic component, such as an integrated circuit chip, having a first pattern of contact sites and includes a substrate having a second pattern of contact sites corresponding to the first pattern. The electronic component is demountably connected to the substrate by a bump-and-socket arrangement at each pair of contact sites. One of the contact sites has a raised bump that is received within a depressed area of the other contact site. The raised bumps are pressed into the depressed areas, forming a ring of contact to electrically and mechanically connect the electronic component to the substrate. Preferably, the depressed areas are formed in a compliant material that allows some deformation but not so much as to allow the raised bumps to bottom out against the depressed areas. The assembly may be used in forming multi-chip modules having demountable integrated circuit chips.

REFERENCES:
patent: 4545610 (1985-10-01), Lakritz et al.
patent: 4617730 (1986-10-01), Geldermans et al.
patent: 4940181 (1990-07-01), Juskey, Jr. et al.
patent: 5065280 (1991-11-01), Karnezos et al.
patent: 5142444 (1992-08-01), Matta et al.

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