Compression/decompress with ECC data flow architecture

Details Compression/decompress with ECC data flow architecture Compression/decompress with ECC data flow architecture

1990-11-13

1994-03-08

Nguyen, Hoa T.

Excavating

364401, 395575, G06F 1110

Patent

active

052933881

ABSTRACT:
An architecture for providing hardware compression/decompression with ECC to data flow in a computer system utilizes a hardware implementation of the compression/decompression circuit in a peripheral adapter of one of many peripheral devices. Error correction coding is provided by software in the host RAM. The compression/decompression circuit can be located in the periphery and can service a number of peripheral devices. The CPU and DMA controller in the host computer are capable of providing concurrent processing for hard disk operation, peripheral control (such as a tape or a modem), compression/decompression of data, and error correction coding of the compressed data. This significantly speeds up the performance of the computer system.

REFERENCES:
patent: 5128859 (1992-07-01), Carbone et al.

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