Compressed instruction format for use in a VLIW processor and pr

Details Compressed instruction format for use in a VLIW processor and pr Compressed instruction format for use in a VLIW processor and pr

1998-05-29

1999-03-02

Coleman, Eric

395705, G06F 700

Patent

active

058782672

ABSTRACT:
Software creates a compressed instruction format for a VLIW processor which allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.

REFERENCES:
patent: 4437149 (1984-03-01), Pomerene
patent: 5057837 (1991-10-01), Colwell
patent: 5179680 (1993-01-01), Colwell
patent: 5632024 (1997-05-01), Yajima
patent: 5652852 (1997-07-01), Yokota

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