Compressed Instruction format for use in a VLIW processor

Details Compressed Instruction format for use in a VLIW processor Compressed Instruction format for use in a VLIW processor

1996-05-15

1998-10-20

Pan, Daniel H.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358432, 36472503, G06F 1204, G06F 922, H03M 730

Patent

active

058260544

ABSTRACT:
A compressed instruction format for a VLIW processor allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.

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