Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-09-14
2002-02-05
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185290, C365S185110, C365S218000
Reexamination Certificate
active
06345001
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to event counting techniques, and, more specifically, to the application of such techniques to semiconductor memory systems, particularly to non-volatile flash electrically-erasable and programmable read-only memories (EEPROMs).
Flash EEPROM systems are being used in a wide variety of applications, particularly when packaged in an enclosed card that is removably connected with a host system. Current commercial memory card formats include that of the Personal Computer Memory Card International Association (PCMCIA), CompactFlash (CF), MultiMediaCard (MMC) and Secure Digital (SD). One supplier of these cards is SanDisk Corporation, assignee of this application. Host systems with which such cards are used include personal computers, notebook computers, hand held computing devices, cameras, audio reproducing devices, and the like. Flash EEPROM systems are also utilized as bulk mass storage embedded in host systems.
Such non-volatile memory systems include an array of memory cells, peripheral operating circuits and a system controller. The controller manages communication with the host system and operation of the memory cell array to store and retrieve user data. The memory cells are grouped together into blocks of cells, a block of cells being the smallest grouping of cells that are simultaneously erasable. Prior to writing data into one or more blocks of cells, those blocks of cells are erased. User data are typically transferred between the host and memory array in sectors. A sector of user data can be any amount that is convenient to handle, preferably less than or equal to the capacity of the memory block, often being equal to the standard disk drive sector size, which is 512 bytes.
In one commercial architecture, the memory system block is sized to store one sector of user data plus overhead data, the overhead data including information such as an error correction code (ECC) for the user data stored in the block, a count of the number of times that the block has been erased and reprogrammed, defects and other physical information of the memory cell block, and programming and/or erase voltages to be applied to the block. Various implementations of this type of non-volatile memory system are described in the following United States patents and pending applications, each of which is incorporated herein in its entirety by this reference: U.S. Pat. Nos. 5,172,338, 5,602,987, 5,315,541, 5,200,959, 5,270,979, 5,428,621, 5,663,901, 5,532,962, 5,430,859 and 5,712,180, and patent applications Ser. Nos. 08/910,947, filed Aug. 7, 1997, and 09/343,328, filed Jun. 30, 1999. In another commercial architecture, the overhead data for a large number of blocks storing user data are stored together within tables in other blocks. This overhead data includes a count of the number of times that individual user data blocks have been erased and reprogrammed. An example of such a system is described in U. S. patent application Ser. No. 09/505,555, filed Feb. 17, 2000. Yet another type of non-volatile memory system utilizes a larger memory cell block size that stores multiple sectors of user data.
The number of erase/reprogramming cycles experienced by individual memory blocks (their “experience count”) is often maintained within a flash memory system for one or more reasons. One reason is to determine when a block is reaching its end of lifetime, in order to replace it with another block by mapping it out of the system before it fails from overuse. This is described in U.S. Pat. No. 5,043,940, for example, which patent is incorporated herein by this reference. Current commercial floating gate memory cells have a lifetime of from several hundred thousand to one million erase/reprogramming cycles, which is often larger than any of the blocks are cycled in most applications during the useful life of the memory. However, other more reprogramming intensive applications can reach such numbers. Another reason for keeping track of the block experience counts is to be able to alter the mapping of data into the various blocks in order to even out their wear before they reach their ends of lifetime as a way of extending the life of the memory system. Examples of such wear leveling techniques are given in U.S. Pat. No. 6,081,447, which patent is incorporated herein in its entirety by this reference. Yet another reason for maintaining block experience counts is to be able to adjust programming and other operating voltages to take into account changes in characteristics of the memory cells that occur as the number of erase/reprogramming cycles increases.
SUMMARY OF THE INVENTION
Rather than keeping track of each occurrence of an event, it is noted only each time a large number of events has occurred. One advantage is that a compressed count R, representative of the number of events A that has occurred, needs to be updated less frequently than if each of the events is counted. Another advantage is that, in a binary counting system, a fewer number of bits are required to maintain a count R that is representative of a larger number of events A. A preferred technique for maintaining the compressed count R includes establishing some probability P that the compressed count R will be updated each time that the event being monitored occurs. This results in updating the compressed count R, on average, once every 1/P number of actual events. This probability is preferably chosen to be as independent of the operation of a system in which the events are occurring as is practical, so that the influence of the system operation upon the frequency of updating the compressed count R is minimized.
In the specific examples described herein, this technique is utilized to monitor the number of some repetitive event that occurs as part of operating an electronic system. A random number generator is preferred for use to determine when the compressed count R of the number of events is updated, a pseudo-random number generator usually being used in practice. A random number is generated when the event occurs, preferably each time the event occurs. One of the random numbers is preferably designated as a trigger to cause the compressed count R to be updated, such as by being incremented to the next number in order. This will occur, on the average, once every N events, where N is the total possible number of distinct random numbers that is generated over time by the random number generator. Rather than each occurrence of the event being counted, therefore, the compressed count R is updated on average once every N events, and that count represents 1/N the number of events that have occurred, on average. Or, to say it in a different way, the probability P that any one occurrence of an event will result in the compressed count R being updated is 1/N. A product of R and N gives the number of actual events A that has occurred, if that is needed, within a margin of probable error that is proportional to 1/P, which is to say that the likely error goes up as N goes up since P=1/N.
These techniques have particular application to digital memory systems. In the example of non-volatile flash memory systems described in the Background above, updating the compressed count R of an event, such as the erase/reprogramming event, need occur less frequently, so less time is taken away from other operations of the memory. This results in such other operations, such as user data programming, occurring faster. The number of bits required to store the count for each of the blocks is also significantly reduced. Further, the complexity of the operation of the memory system is reduced when each occurrence of the event need not be counted.
In an application of this technique to maintain an experience count (sometimes called a “hot” count) of the number of erasures and reprogramming cycles occurring in a flash memory, the number N is selected to be a small fraction of M, where M is the expected life of the memory in terms of a maximum number of erase/reprogramming cycles that a memory cell can safely exp
Lam David
Nelms David
Parsons Gerald P.
SanDisk Corporation
Skjerven Morrill & MacPherson LLP
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