Boots – shoes – and leggings
Patent
1990-06-29
1992-06-02
Lall, Parshotam S.
Boots, shoes, and leggings
364488, G06F 1560
Patent
active
051193132
ABSTRACT:
Random logic circuitry (210) is laid out in a logic array (212) that has a plurality of row and column locations. The logic circuitry (210) implements a plurality of dynamic logic circuits, each logic circuit having a plurality of logic gate field effect transistors (224) each formed at a selected intersection of one of the row locations and a predetermined plurality of the column locations. Elongate gate conductors (584-602) are formed at selected row locations in the logic array (212), each gate conductor provided as a gate for one or more of the logic gate transistors (224). Selected ones (e.g. 514, 544) of the transistors are merged in a row direction if the logic does not require them to be isolated from one another. A plurality of elongate second conductors (222) interconnect to selected ones of the sources or drains of the transistors (224). Non-Boolean portions of the logic circuitry are formed in an adjacent tile section (214) in the semiconductor layer separate from the logic array (212). A plurality of river-routed conductors (e.g. AL, F, LL) each connect together a respective array terminal (710, 712), and a terminal of a respective non-Boolean tile.
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Bosshart Patrick
Houston Theodore W.
Kalyan Vibhu
Matzke Douglas
Shaw Ching-Hao
Bassuk Lawrence J.
Brady III W. James
Cosimano Edward R.
Donaldson Richard L.
Lall Parshotam S.
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