Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device
Reexamination Certificate
2002-12-13
2004-09-07
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
C257S200000, C257S201000
Reexamination Certificate
active
06787817
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device which is represented by HEMT (High Electron Mobility Transistor) and the method of manufacturing thereof.
2. Description of the Related Art
In recent years, wireless LAN (Local Area Network) and equipment such as an automobile radar using a millimeter wave (a 30 to 300 GHz frequency band) and a sub-millimeter wave (several to 30 GHz frequency band) have been developed increasingly. In the wireless LAN and the equipment such as an automobile radar, a high output amplifier is used as their component. Since the high output amplifier performs a high output operation, a semiconductor device as its basic device is required to have a high breakdown voltage.
As a technique related to improvement in high breakdown voltage of HEMT, one of semiconductor devices for such application, Japanese Published Unexamined Patent Application No. Hei 4-186845 (a prior art example 1) discloses a field-effect transistor (FET) of an offset construction which improves reproducibility of breakdown voltage between gate and drain and mass productivity to provide high gain. In addition, Japanese Published Unexamined Patent Application No. Hei 6-21101 (a prior art example 2) discloses a Schottky gate type field-effect transistor in which a convex part is provided in a recess region between a gate electrode and a drain electrode, a recess width is shortened in a dummy manner to provide high output, and the gap between the electrodes is increased for improvement in high breakdown voltage.
Japanese Published Unexamined Patent Application No. Hei 8-274118 (a prior art example 3) discloses a field-effect type semiconductor device which releases local electric field concentration to improve a breakdown voltage and eliminates variation in high frequency characteristic due to variation in mask alignment. Japanese Published Unexamined Patent Application No. Hei 10-214848 (a prior art example 4) discloses a field-effect transistor which can reduce parasitic capacitance and drain conductance and is hard to cause a short channel effect.
SUMMARY OF THE INVENTION
In the above prior art examples 1 to 4, the breakdown voltage in the on state described later in embodiments is low as about 10V and a drain voltage margin to breakdown is small. The drain breakdown voltage margin is insufficient. Since the drain voltage margin is small, the examples are weak to breakdown due to a surge voltage. They cannot be applied to all high frequency systems typically used and are limited.
An object of the present invention is to provide a semiconductor device which has small variation in manufacture, can reduce the manufacturing cost and has high frequency and high breakdown voltage characteristics. Another object of the present invention is to provide the method of manufacturing thereof.
The above objects can be achieved by the following semiconductor devices As shown in
FIG. 1
as an essential part, sectional diagram of a semiconductor device of the present invention, a semiconductor device in which on a semiconductor substrate
1
, a buffer layer
2
, a channel layer
3
, a first conductivity type carrier providing layer
4
and a barrier layer
5
are formed from the side of the semiconductor substrate
1
, and a source electrode
8
, a drain electrode
9
, a gate electrode
10
between the source electrode
8
and the drain electrode
9
, an ohmic layer
6
connected electrically to the source electrode
8
, and an ohmic layer
7
connected electrically to the drain electrode
9
are formed, wherein a region
11
including a first conductivity type high impurity concentration semiconductor and a region
12
including a first conductivity type low impurity concentration semiconductor are formed from the side of the ohmic layer
7
at the side far from the semiconductor substrate
1
of the end surface of the barrier layer
5
opposite the semiconductor substrate
1
and between the ohmic layer
7
and the gate electrode
10
, the sheet impurity concentration of the region
12
including a low impurity concentration semiconductor is lower than that between the bottom surface of the gate electrode
10
at the side of the semiconductor substrate
1
and the end surface of the channel layer
3
opposite the semiconductor substrate
1
, and the sheet impurity concentration of the region
11
including a high impurity concentration semiconductor is higher than that of the region
12
including a low impurity concentration semiconductor. In addition, as shown in
FIG. 2
as an essential part, plan view of the semiconductor device of the present invention, the region
11
including a high impurity concentration semiconductor and the region
12
including a low impurity concentration semiconductor are formed consecutively between one end surface
20
of an operating region of the semiconductor device and the other end surface
21
facing the end surface
20
, respectively.
FIG. 1
is a sectional view taken along line I-I′ of FIG.
2
. The reference numeral
30
of
FIG. 2
denotes a wiring connection pad part of the gate electrode
10
. In
FIGS. 1 and 2
, the wiring is omitted.
Further, the above objects can be achieved by the method of manufacturing the semiconductor device including the steps of: stacking, on a semiconductor substrate
1
, a buffer layer
2
, a channel layer
3
, a first conductivity type carrier providing layer
4
, a barrier layer
5
, an ohmic layer
6
and a first conductivity type ohmic layer
7
from the side of the semiconductor substrate
1
; forming a source electrode
8
and a drain electrode
9
; processing the first conductivity type ohmic layer to form the ohmic layer
6
connected electrically to the source electrode
8
and the ohmic layer
7
connected electrically to the drain electrode
9
; forming, between a gate electrode
10
formed in the later step and the ohmic layer
7
, a region
12
including a low impurity concentration semiconductor having a sheet impurity concentration lower than that between the bottom surface of the gate electrode
10
at the side of the semiconductor substrate
1
and the end surface of the channel layer
3
opposite the semiconductor substrate
1
so as to be consecutive between one end surface
20
of an operating region of the semiconductor device and the other end surface
21
facing the end surface; forming, between the gate electrode
10
and the region
12
, a region
11
including a high impurity concentration semiconductor having a sheet impurity concentration higher than that of the region
12
so as to be consecutive between one end surface
20
of an operating region of the semiconductor device and the other end surface
21
facing the end surface
20
; and forming the gate electrode
10
.
The above objects and other objects of the present invention will be apparent by the following detailed description and the attached claims with reference to the accompanying drawings.
REFERENCES:
patent: 4-186845 (1992-07-01), None
patent: 06-021101 (1994-01-01), None
patent: 08-274118 (1996-10-01), None
patent: 10-214848 (1998-08-01), None
“Physics of Semiconductor Devices (Second Edition)” S.M. Sze, p. 45, p. 14 lines 10-14.
“High Performance In0.5A10.5As/In0.5Ga0.5As High Electron Mobility Transistors on GaAs” Jpn. J. Appl. Phys. vol. 35 (1996) pp. 5642-5645, Part 1, No. 11, November 1996—cited on p. 24, lines 12-14.
Kobayashi Masayoshi
Takatani Shinichiro
Takazawa Hiroyuki
Yamane Masao
Abraham Fetsum
Antonelli Terry Stout & Kraus LLP
Renesas Technology Corporation
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