Compound semiconductor field-effect transistor with improved cur

Details Compound semiconductor field-effect transistor with improved cur Compound semiconductor field-effect transistor with improved cur

1997-09-30

2000-09-19

Loke, Steven H.

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Field effect transistor

257194, H01L 310328

Patent

active

061216410

ABSTRACT:
A p-type layer which is not depleted is inserted in a position at a depth relative to a lower surface of a gate electrode that is less than three times the distance between a lower surface of a gate electrode and a channel layer. A drain voltage at which the p-type layer is depleted is higher than a drain voltage at which a speed of electrons is saturated for thereby shielding traps while suppressing a drain parasitic capacitance and a short channel effect.

REFERENCES:
patent: 5389802 (1995-02-01), Ohno
Y. Ohno, "Short-Channel MOSFET V.sub.T -V.sub.DS Characteristics Model Based on a Point Charge and Its Mirror Images", IEEE Transactions on Electron Devices, vol. ED-29, No. 2, Feb. 1982, pp. 211-216.
M. Nogome et al., "Shielding Effects of Drain Lag Phenomena by a p-Buffer Layer", Electronics Information Communications Society, 1996, pp. 101.

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