Compound semiconductor field effect transistor

Details Compound semiconductor field effect transistor Compound semiconductor field effect transistor

2001-03-02

2003-03-18

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Specified wide band gap semiconductor material other than...

C257S194000, C257S200000, C257S201000, C438S285000, C438S590000

Reexamination Certificate

active

06534790

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a field effect transistor (FET) and more particularly to a heterojunction FET.
2. Description of the Related Art
A heterojunction FET of which a HEMT (High Electron Mobility Transistor) with a GaAs-based or InP-based group III-V compound semiconductor is typical has been being employed as a low-noise high-output high-efficiency high-frequency device for various purposes.
FIG. 61
is, for example, a cross-sectional view of the structure of a FET shown in Japanese Patent Application Laid-open No. 64924/1998. In
FIG. 61
, referential numeral
1005
indicates a semi-insulating GaAs substrate;
1004
, a buffer layer formed on the semi-insulating GaAs substrate
1005
;
1003
, an n-GaAs active layer formed in a prescribed region of the buffer layer
1004
;
1007
, an n
+
ohmic contact region formed in a region of the buffer layer
1004
where no n-GaAs active layer
1003
is formed;
1002
, an n-AlGaAs etching stopper layer formed on the n-GaAs active layer
1003
;
1001
, an i-GaAs layer formed in a prescribed region of the n-AlGaAs etching stopper layer
1002
;
1008
, an SiO
2
insulating film formed on the i-GaAs layer
1001
;
1015
and
1016
, source/drain electrodes made of AuGe-based metal, being formed on the n
+
ohmic contact region
1007
; and
1017
, a gate layer made of a p
+
-type semiconductor. Such a FET having a p-n junction in a gate region as described above is known as a JFET (Junction Field Effect Transistor). Therein, the p-n junction is biased and the drain current is controlled through the adjustment of the width of the space charge region directly under the gate.
Next, referring to
FIGS. 62-64
, a method of manufacturing the afore-mentioned semiconductor device is described. In the first step thereof, layers
1001
-
1005
are formed by the epitaxial crystal growth method, in succession. An n
+
ohmic contact region
1007
is then formed in each prescribed region on the i-GaAs layer
1005
, using the ion-implantation/annealing method. After that, over the entire surface of the semiconductor substrate, an SiO
2
insulating film
1008
is deposited and, using resist masks
1009
, an opening is made in the SiO
2
film
1008
. Further, the i-GaAs layer
1001
is dry etched and thereby a gate region is formed (FIG.
62
).
Next, a semiconductor layer
1017
of p
+
-type conductivity is formed in the gate region by either an MOCVD (Metal Organic Chemical Vapour Deposition) method or a CBE (Chemical Beam Epitaxy) method, using the SiO
2
insulating film
1008
as a mask (FIG.
63
). After that, using a photoresist
1014
as a mask, openings for source/drain electrode formation sections are made in the SiO
2
insulating film
1008
(FIG.
64
), and then, using the same photoresist
1014
, a drain electrode
1015
and a source electrode
1016
of AuGe-based metal are formed by the deposition/lift-off method, whereby a semiconductor device shown in
FIG. 61
is obtained.
The structure of a conventional semiconductor device and the procedure of a manufacturing method thereof are as described above. However, in forming a semiconductor layer of p
+
-type conductivity, if the formation is made on AlGaAs, the amount of energy discontinuity between the valance bands of AlGaAs and GaAs or those of AlGaAs and InGaAs is small so that, with an applied voltage, holes are made to pour forth, which leads to deterioration of withstand voltage characteristic and unstabilization of operations in the FET.
Further, since Al is easily oxidized to form a thin natural oxidation film, the morphology of the p
+
-type semiconductor is considerably inferior in quality. Moreover, when a p
+
-type semiconductor is formed on AlGaAs, numerous interface states turn up on the interface therebetween. Due to these factors, when such a semiconductor device is utilized as a high-frequency device, high frequency characteristic thereof markedly deteriorates.
In addition, because the surface of the AlGaAs layer on which the p
+
-type semiconductor is grown is formed by dry etching, some damage is produced on the AlGaAs layer. Yet, the selectivity of this dry etching method between these two substances is not particularly good. This brings about deterioration of high-frequency characteristic as well as dispersion of various characteristics of the FET when fabricated.
Electrical resistances that arise in various sections of a FET by way of distributed constants include contact resistances from respective ohmic electrodes to the channel layer and a sheet resistance under the gate. Meanwhile, ON-resistance of a FET is the whole resistance from the source electrode to the drain electrode. As mentioned in IEEE GaAs IC Symposium, pp. 119 (1996), a low ON-resistance is essential to attain a high output and a high efficiency in low-voltage operations. Nevertheless, contact resistances from the ohmic electrodes to the channel layer in conventional structures are notably high.
SUMMARY OF THE INVENTION
An object of the present invention is to improve withstand voltage characteristic of a JFET and realize stable operations of a JFET.
Another object of the present invention is to achieve better morphology in forming a semiconductor of p
+
-type conductivity and suppress substantially creation of the interface states and thereby enhance high frequency characteristic.
A further object of the present invention is to improve a method of manufacturing a semiconductor substance and thereby reduce deterioration of high frequency characteristic as well as dispersion of various characteristics of JFET when fabricated.
A still further object of the present invention is to change the epitaxial structure and thereby lower the contact resistance from the cap layer to the channel layer.
A still further object of the present invention is to achieve a structure over which control can be easily made in forming semiconductor substances.
A still further object of the present invention is to provide a manufacturing method of a FET wherein, in gate formation, structure control is easy and good uniformity is obtainable.
The present invention relates to a field effect transistor having, on a semi-insulating compound semiconductor substrate:
a buffer layer;
an active layer that includes a channel layer made of a first conductive-type epitaxial growth layer;
source/drain electrodes formed on a first conductive-type semiconductor ohmic contact layer which is formed either on said active layer or on a lateral face thereof;
a gate layer made of a second conductive-type epitaxial growth layer; and
a gate electrode formed on said gate layer; which further has:
between said second conductive-type gate layer and said channel layer, a semiconductor layer (referred to as “energy discontinuity layer”, hereinafter) that rapidly lowers the energy of the valance band spreading from said gate layer to said channel layer.
The present invention provides a field effect transistor; wherein:
(1) said energy discontinuity layer is made of InGaP;
(2) said first conductive-type is n-type and second conductive-type is p-type;
(3) said channel layer is composed of either InGaAs or GaAs and said second conductive-type gate layer is a layer composed of substances selected from the group consisting of GaAs, AlGaAs, InGaAs and InGap.
(4) a semiconductor layer to form a first recess is formed on said energy discontinuity layer and another semiconductor layer to form a second recess which is wider than said first recess is formed on said semiconductor layer to form a first recess, and said second conductive-type gate layer is formed in the first recess;
(5) the ohmic contact layer to provide ohmic contacts for source/drain electrodes is formed on said energy discontinuity layer and said second conductive-type gate layer is formed within a one-stage recess formed with said ohmic contact layer;
(6) while as described in (5), the ohmic contact layer is formed by regrowth on said energy discontinuity layer;
(7) while as described in (5),

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