Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Compound semiconductor
Reexamination Certificate
2000-11-14
2003-09-30
Loke, Steven (Department: 2811)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
Compound semiconductor
C438S047000, C438S572000, C438S606000, C257S194000
Reexamination Certificate
active
06627473
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a compound semiconductor and, more particularly, to a compound semiconductor device having an etching stopper layer between an active layer and an ohmic electrode.
DESCRIPTION OF THE RELATED ART
A heterojunction metal-semiconductor field effect transistor is a typical example of the compound semiconductor device. The high electron mobility transistor is a kind of heterojunction metal-semiconductor field effect transistor, and is featured by an inversion layer at the boundary between an electron supply layer and a channel layer. The heterojunction metal-semiconductor field effect transistor finds a wide variety of application such as, for example, a DBS ( Direct Broadcasting Satellite). The compound semiconductor device is expected to have low-noise characteristics and achieve a high-gain.
In order to enhance the mutual conductance, it is known to increase the dopant impurity in the electron supply layer. Reduction of source resistance is also appropriate. However, when the dopant concentration is uniformly increased in the electron supply layer, a problem is encountered in the hetero-junction metal-semiconductor field effect transistor in low withstand voltage between the gate electrode and the electron supply layer.
A stepped doping concentration structure has been proposed. When the stepped dopant concentration structure is applied to the electron supply layer, the electron supply layer has a relatively heavy dopant concentration close to the channel layer and a relatively light dopant concentration close to the gate electrode.
FIG. 1
illustrates the prior art high electron mobility transistor with the stepped dopant concentration structure. The prior art high electron mobility transistor is fabricated on a semi-insulating substrate
1
, which is formed of gallium arsenide. The prior art high electron mobility transistor comprises a buffer layer
2
, a channel layer
3
, an electron supply layer
4
/
5
, cap layers
8
, ohmic electrodes
9
and a gate electrode
10
. Gallium arsenide is epitaxially grown on the semi-insulating substrate
1
, and forms a gallium arsenide layer. The gallium arsenide layer serves as the buffer layer
2
. On the gallium arsenide layer is epitaxially grown indium gallium arsenide which forms an indium gallium arsenide layer serving as the channel layer
3
. Heavily-doped n-type aluminum gallium arsenide, i.e., n
+
Al
0.2
Ga
0.8
As and lightly-doped n-type aluminum gallium arsenide, i.e., n
−
Al
0.2
Ga
0.8
As are successively epitaxially grown to 10 nanometers thick and 20 nanometers thick on the indium gallium arsenide layer, and form a heavily-doped n-type aluminum gallium arsenide layer
4
and a lightly-doped n-type aluminum gallium arsenide layer
5
. The dopant concentration is 4×10
−18
/cm
3
(4× 10
−18
/cm
3
) in the heavily-doped n-type aluminum gallium arsenide layer
4
and 1×10
17
/cm
3
in the lightly-doped n-type aluminum gallium arsenide layer
5
. The heavily-doped n-type aluminum gallium arsenide layer
4
and the lightly-doped n-type aluminum gallium arsenide layer
5
form in combination the electron supply layer
4
/
5
. The heavily-doped n-type aluminum gallium arsenide layer
4
is contiguous to the channel layer
3
, and the gate electrode
10
is held in contact with the lightly-doped n-type aluminum gallium arsenide layer
5
. The n-type dopant concentration is changed at the boundary between the heavily-doped n-type aluminum gallium arsenide layer
4
and the lightly-doped n-type aluminum gallium arsenide layer
5
. Thus, the electron supply layer
4
/
5
has the stepped dopant concentration structure.
On the lightly-doped aluminum gallium arsenide layer
5
is epitaxially grown heavily-doped n-type gallium arsenide from which forms the cap layers 8 of 80 nanometers thick are formed. The dopant concentration is 3×10
18
/cm
3
in the heavily-doped n-type gallium arsenide layer. Namely, the heavily-doped n-type gallium arsenide layer is partially etched so as to expose the electron supply layer
4
/
5
to a recess between the cap layers
8
. The gate electrode
10
is held in contact with the exposed portion to the electron supply layer
5
. On the other hand, the ohmic electrodes
9
are held in contact with the cap layers on both sides of the recess, and serve as a source electrode and a drain electrode.
The prior art high electron mobility transistor achieves a large mutual conductance by virtue of the heavily-doped n-type aluminum gallium arsenide layer
4
as well as a high withstand voltage by virtue of the lightly-doped n-type aluminum gallium arsenide layer
5
. However, the threshold voltage and, accordingly, the amount of channel current are liable to fluctuate among the products. This is because of the fact that the etchant is liable to partially remove the lightly-doped n-type aluminum gallium arsenide layer
5
during the formation of the recess.
An etching stopper has been proposed as a countermeasure against the problem. The recess is formed by using mixture of citric acid and H
2
O
2
as wet etchant. Upon completion of the fabrication process, the prior art high electron mobility transistor has the structure shown in FIG.
2
.
The prior art high electron mobility transistor is fabricated on a semi-insulating substrate
1
, which is formed of gallium arsenide. The prior art high electron mobility transistor comprises a buffer layer
2
, a channel layer
3
, an electron supply layer
4
/
5
, etching stopper layers
7
, cap layers
8
, ohmic electrodes
9
and a gate electrode
10
. Gallium arsenide is epitaxially grown on the semi-insulating substrate
1
, and forms a gallium arsenide layer. The gallium arsenide layer serves as the buffer layer
2
. On the gallium arsenide layer is epitaxially grown indium gallium arsenide which forms an indium gallium arsenide layer serving as the channel layer
3
. Heavily-doped n-type aluminum gallium arsenide, i.e., n
+
Al
0.2
Ga
0.8
As and lightly-doped n-type aluminum gallium arsenide, i.e., n
−
Al
0.2
Ga
0.8
As are successively epitaxially grown to 10 nanometers thick and 20 nanometers thick on the indium gallium arsenide layer, and form a heavily-doped n-type aluminum gallium arsenide layer
4
and a lightly-doped n-type aluminum gallium arsenide layer
5
. The dopant concentration is 4×10
18
/cm
3
in the heavily-doped n-type aluminum gallium arsenide layer
4
and 1×10
17
/cm
3
in the lightly-doped n-type aluminum gallium arsenide layer
5
. The heavily-doped n-type aluminum gallium arsenide layer
4
and the lightly-doped n-type aluminum gallium arsenide layer
5
form in combination the electron supply layer
4
/
5
. The heavily-doped n-type aluminum gallium arsenide layer
4
is contiguous to the channel layer
3
, and the gate electrode
10
is held in contact with the lightly-doped n-type aluminum gallium arsenide layer
5
. The n-type dopant concentration is changed at the boundary between the heavily-doped n-type aluminum gallium arsenide layer
4
and the lightly-doped n-type aluminum gallium arsenide layer
5
. Thus, the electron supply layer
4
/
5
has the stepped dopant concentration structure.
On the lightly-doped aluminum gallium arsenide layer
5
is grown lightly-doped n-type aluminum gallium arsenide n
−
Al
0.7
Ga
0.3
As which forms a lightly-doped n-type aluminum gallium arsenide layer. The etching stopper layers
7
are formed from the lightly-doped n-type aluminum gallium arsenide layer. Heavily-doped n-type gallium arsenide is epitaxially grown to 80 nanometers thick on the lightly-doped n-type aluminum gallium arsenide layer
7
, and forms a heavily-doped n-type gallium arsenide layer. The cap layers
8
are formed from the heavily-doped n-type gallium arsenide layer. The dopant concentration is 3×10
18
/cm
3
in the heavily-doped n-type gallium arsenide layer. The heavily-doped n-type gallium arsenide layer
8
and the lightly-doped aluminum gallium arsenide layer
7
are partially etched so as to expose the elec
Negishi Hitoshi
Oikawa Hirokazu
Gebremariam Samuel A
Loke Steven
McGinn & Gibb PLLC
NEC Compound Semiconductor Devices Ltd.
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