Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
2000-01-27
2002-05-21
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
C257S197000, C257S198000, C257S472000
Reexamination Certificate
active
06392262
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a compound semiconductor device and, more particularly, to a compound semiconductor device with improved ohmic electrodes and a process for producing an ohmic electrode incorporated in the compound semiconductor device.
DESCRIPTION OF THE RELATED ART
A hetero-junction bipolar transistor is an example of the compound semiconductor device. Several III-V compound semiconductor materials are used in the hetero-junction bipolar transistor, and electrodes form ohmic contacts together with one of the III-V compound semiconductor materials. Research and development efforts have been made for improvement in the heterojunction bipolar transistor. In order to enhance the stability and the reliability of the hetero-junction bipolar transistor, it is necessary to improve the contact resistance and the thermal stability of the ohmic contacts.
Conventionally, when the ohmic contact is formed on a p-type GaAs layer, a AuZn/Au laminated structure, a AuBe/Au laminated structure, a AuMn/Au laminated structure, a AuMg/Au laminated structure and Cr/Au laminated structure are popular to the electrode. However, these laminated structures are large in contact resistance and thermally unstable. The low thermal stability is derived from the gold, which is reactive with the gallium arsenide.
The ohmic contact is formed through the following processes. The first prior art process is disclosed by Takahashi in Japanese Patent Publication of Unexamined Application No. 5-259435.
FIGS. 1A and 1B
illustrate the first prior art process. The first prior art process starts with preparation of a semi-insulating GaAs substrate
100
. A p-type GaAs layer
101
is grown on the semi-insulating GaAs substrate
100
. A metal layer
102
of Pd, a metal layer
103
of Zn, a metal layer
104
of Pt and a metal layer
105
of Au are successively laminated over the p-type GaAs layer
101
as shown in FIG.
1
A.
Subsequently, the resultant structure is subjected to a heat treatment at 300 degrees in centigrade. Pd reacts with GaAs in the heat treatment, and Pd and GaAs produce Pd-GaAs alloy layer
106
under the Pd layer
102
. Moreover, Zn is diffused from the metal layer
103
into the p-type GaAs layer
101
, and forms a heavily-doped p-type GaAs layer
107
under the Pd-GaAs alloy layer
106
. The heavily-doped p-type GaAs layer
107
offers an ohmic contact. The metal layer
104
of Pt does not allow Au to be diffused into the p-type GaAs layer
101
, and serves as a barrier layer against Au. This results in improvement in thermal stability.
The second prior art process is disclosed by Okada et al. in Japanese Journal of Applied Physics, 30, L558-L560 (1991).
FIGS. 2A and 2B
illustrate the second prior art process. The second prior art process starts with preparation of a semi-insulating GaAs substrate
100
. A p-type GaAs layer
101
is grown on the semi-insulating GaAs substrate
100
. A metal layer of Pt
108
, a metal layer
109
of Ti, a metal layer
108
a
of Pt and a metal layer
110
of Au are successively laminated over the p-type GaAs layer
101
.
Subsequently, the resultant structure is treated with heat. Namely, the resultant structure is heated to 400 degrees in centigrade, and is maintained in the high-temperature atmosphere for one minute. Pt reacts with GaAs, and Pt and GaAs produce a Pt-GaAs alloy layer
111
. The Schottky barrier between Pt and p-type GaAs is low enough to form a low-resistive ohmic contact. The metal layer
108
a
of Pt blocks the p-type GaAs layer
101
from Au during the heat treatment, and, accordingly, the thermal stability is improved.
The present inventor had disclosed the third prior art process in Japanese Patent Application, which was published in 1998 as Japanese Patent Publication of Unexamined Application No. 10-144622. The third prior art process comprises the steps of successively forming a first layer, a second layer and a third layer on a substrate of III-V compound semiconductor and treating the resultant structure with heat in reducing gas. The third layer is formed of a first element, which serves as an n-type dopant impurity in the III-V compound semiconductor. The second layer is formed of a second element, which decreases the potential barrier height between the III-V compound semiconductor and metal. The first layer is formed of a third element, which reacts with the first element for producing a refractory alloy. An ohmic electrode is obtained through the heat treatment. The ohmic electrode and the n-type GaAs layer form ohmic contact, which is small in contact resistance. When many ohmic electrodes are formed on the substrate
100
, the contact resistance is uniform between the ohmic contacts. Furthermore, the contact resistance between the lots falls within a narrow range.
Although the metal layer
104
/
108
a
of Pt is formed under the metal layer
105
/
110
of Au, the metal layer
104
/
108
a
can not perfectly block the GaAs layer
101
from Au. A small amount of Au penetrates the metal layer
104
/
108
a
, and reaches the p-type GaAs layer
101
in a long operating time. Au atoms react with GaAs. As a result, the prior art compound semiconductor device loses the thermal stability, and the contact resistance is increased. When the prior art ohmic electrode serves as a base electrode of the hetero-bipolar transistor, Au is further diffused through the base region into the collector region, and the collector breakdown voltage is lowered. Thus, the first problem inherent in the first and second prior arts is the imperfect barrier against Au atoms.
Another problem inherent in the first and second prior arts is a relatively high contact resistance. It is difficult to reduce the contact resistance equal to or less than 1×10
−7
&OHgr;cm
2
. Yet another problem encountered in the first and second prior arts is the production cost. The prior art ohmic electrodes require the noble metals, i.e., platinum and gold, and the noble metals increase the production cost.
The ohmic electrode formed through the third prior art process is free from the above-described problems. However, the third prior art process is applicable to the n-type GaAs substrate, only. In other words, the ohmic electrode is not formed on a p-type GaAs layer. Thus, the problem inherent in the third prior art process is the limitation to the conductivity type.
SUMMARY OF THE INVENTION
It is therefore an important object of the present invention to provide a compound semiconductor device, which has an electrode low in contact resistance and thermally stable on a compound semiconductor device regardless of the conductivity type.
It is also an important object of the present invention to provide a process for producing an ohmic contact, which is thermally stable, low in contact resistance and production cost and available for both of an n-type compound semiconductor layer and a p-type compound semiconductor layer.
In accordance with one aspect of the present invention, there is provided a compound semiconductor device comprising a substrate, at least one active layer formed of a first compound semiconductor material capable of producing a first Schottky barrier together with a metal and formed over the substrate and at least one electrode formed on the at least one active layer and including a first layer formed of a second compound semiconductor material containing a first element and the elements of the first compound semiconductor material and capable of producing a second Schottky barrier lower than the first Schottky barrier together with the metal and a second layer formed of an refractory alloy containing the first element and a second element.
In accordance with another aspect of the present invention, there is provided a process for producing an ohmic electrode comprising the steps of a) preparing a multiple-layered structure including a first compound semiconductor capable of producing a first Schottky barrier together with a metal and having a contact area, b) forming a preliminary electrode layer containing a first element and
Chaudhuri Olik
Doan Theresa
NEC Corporation
Rosenman & Colin LLP
LandOfFree
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