Active solid-state devices (e.g. – transistors – solid-state diode – Schottky barrier – In integrated structure
Reexamination Certificate
2000-11-09
2003-02-25
Le, Vu A. (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Schottky barrier
In integrated structure
C257S197000
Reexamination Certificate
active
06525388
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a compound semiconductor device and, more particularly, to a compound semiconductor device having a bipolar transistor such as, for example, a heterojunction bipolar transistor.
DESCRIPTION OF THE RELATED ART
Various kinds of compound semiconductor such as, for example, gallium arsenide are used for fabricating electric components. A bipolar transistor is one of the electric components, and the electric components are usually fabricated on a semi-insulating substrate. Surge is unavoidable, and carriers are generated due to the surge. Since the semi-insulating substrate does not provide any discharging path to the carriers, the carriers are liable to be accumulated in the bipolar transistor. The accumulated carriers enhance the current gain, and this phenomenon is equivalent to prolongation of the life time of the minority carriers in the base region. These minority carriers give rise to increase of the majority carrier flowing into the base region. The emitter-base junction has a low breakdown voltage, and the surge is causative of the breakdown of the emitter-base junction. When the surge positively biases the emitter region with respect to the collector region, an extremely large amount of current flows between the emitter region and the collector region through the base region, and gives rise to serious stress. This means that the bipolar transistor requires surge withstand capability.
Several countermeasures have been proposed. One of the countermeasures is disclosed in Japanese Patent Publication of Unexamined Application No. 62-244172.
FIGS. 1 and 2
show the first prior art semiconductor device disclosed in Japanese Patent Publication of Unexamined Application No. 62-244172. The first prior art semiconductor device includes a bipolar transistor and a diode connected between the base region and the collector region.
The first prior art semiconductor device is fabricated on a heavily-doped n-type silicon substrate
31
. A lightly doped n-type epitaxial silicon layer
32
is grown on the major surface of the heavily doped n-type silicon substrate
31
, and serves a the collector region of the bipolar transistor. A lightly-doped p-type silicon layer
33
is formed in the lightly-doped n-type epitaxial silicon layer
32
, and serves as a base region of the bipolar transistor. A heavily-doped p-type silicon region
34
penetrates from the surface of the lightly-doped p-type silicon layer
33
, and serves as a base contact region. A heavily-doped n-type silicon layer
35
is nested in the lightly-doped silicon layer
33
, and is spaced from the heavily-doped p-type silicon region
34
. The heavily-doped n-type silicon layer
35
serves as a multi-emitter region of the bipolar transistor.
A heavily-doped n-type silicon region
36
is further formed in a surface portion of the lightly-doped n-type epitaxial silicon layer
32
, and laterally extends. The heavily-doped n-type silicon region
36
is held in contact with the heavily-doped p-type silicon region
34
, and a Zener diode is implemented. The Zener diode is connected between the base region and the collector region, and prevents the bipolar transistor from the surge.
Another countermeasure is described in Japanese Patent Application No. 11-169321. The invention disclosed in Japanese Patent Application No. 11-169321 was transferred to the assignee of the present invention, and Japanese Patent Application No. 11-169321 will be published in December 2000. The semiconductor device disclosed in Japanese Patent Application No. 11-169321 is hereinbelow referred to as “unpublished semiconductor device”.
The unpublished semiconductor device includes a heterojunction bipolar transistor and a diode connected between the collector region and the emitter region of the heterojunction bipolar transistor. The diode is implemented by a diode-connected heterojunction bipolar transistor, i.e., a heterojunction bipolar transistor having the base region short-circuited with the emitter region. The diode-connected heterojunction bipolar transistor enhances the surge withstand capability.
Yet another countermeasure is disclosed in Japanese Patent Publication of Unexamined Application No. 61-216477. The semiconductor device disclosed in Japanese Patent Publication of Unexamined Application No. 61-216477 is hereinbelow referred to as “second prior art semiconductor device”.
The second prior art semiconductor device includes MOS (Metal-Oxide-Semiconductor) transistors. The MOS transistors form an output driving circuit so as to drive an output terminal. A protective MOS transistor is connected between the output terminal and the ground, and the gate electrode of the protective MOS transistor is grounded. The ground potential keeps the protective MOS transistor off, and the output driving circuit changes the potential level at the output terminal between the positive power voltage and the ground voltage. Surge voltage is assumed to be applied to the output terminal. The surge current flows through the channel of the protective MOS transistor as well as the channel of the MOS transistor forming a part of the output driving circuit. Thus, the protective MOS transistor provides a bypass to the surge current, and prevents the MOS transistor from the damage.
Although the Zener diode is effective against the surge applied between the base region and the collector region, the Zener diode can not prevent the bipolar transistor from surge applied between the emitter region and the collector region. The Japanese Patent Publication of Unexamined Application teaches the Zener diode formed in the epitaxial silicon layer. However, the Japanese Patent Publication of Unexamined Application is silent to a Zener diode to be formed in a semi-insulating substrate used for a compound semi-conductor device. It is impossible to form any heavily-doped impurity region in the semi-insulating substrate. The Japanese Patent Publication of Unexamined Application does not teach how the Zener diode is formed on a semi-insulating substrate. Thus, the countermeasure in the first prior art semiconductor device is not applied to the compound semiconductor device.
Although the unpublished semiconductor device is a kind of compound semiconductor device, the countermeasure disclosed therein does not form any part of the prior art. However, the features of the countermeasure are discussed hereinbelow. First, the protective diode is implemented by the heterojunction bipolar transistor, the base region of which is connected to the emitter region. This means that the protective diode occupies a non-ignoreable amount of real estate. A p-n junction of the heterojunction bipolar transistor serves as the protective diode, and the potential barrier at the p-n junction is higher than a Schottky barrier. As a result, the protective diode has the relatively high turn-on voltage.
The second prior art semiconductor device is equipped with the protective MOS transistor. The protective MOS transistor has the grounded gate electrode, and the surge current flows through the MOS transistor to the ground. The problem inherent in the countermeasure of the second prior art semiconductor device is the occupation area as wide as the MOS transistor forming the part of the output driving circuit. Moreover, the Japanese Patent Publication of Unexamined Application is silent to how the countermeasure is applied to a bipolar transistor of a compound semiconductor device.
Thus, any one of the known countermeasures is not employable in a compound semiconductor device as a countermeasure against the surge applied between the emitter region and the collector region.
SUMMARY OF THE INVENTION
It is therefore an important object of the present invention to provide a compound semiconductor device, which has a countermeasure effective against surge positively biasing an emitter region with respect to a collector region.
To accomplish the object, the present invention proposes to form a Schottky barrier between a collector layer and an emitter signal line.
In accordance wit
Le Vu A.
McGinn & Gibb PLLC
NEC Compound Semiconductor Devices Ltd.
Smith Bradley
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