Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Reexamination Certificate
2001-06-29
2004-09-07
Wilczewsid, Mary (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
C257S191000, C257S197000, C257S198000, C257S475000
Reexamination Certificate
active
06787821
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a compound semiconductor device and, more particularly, a compound semiconductor device having a MESFET.
2. Description of the Prior Art
It is known that, since InGaAs has the large electron mobility, such InGaAs is employed as the channel layer of the MESFET (Metal Semiconductor FET).
The MESFET having the InGaAs channel layer has the structure shown in
FIG. 1A
, for example.
In
FIG. 1A
, a GaAs buffer layer
102
, an n-InGaAs channel layer
103
, and a GaAs barrier layer
104
are formed on a semi-insulating GaAs substrate
101
, and a gate electrode
105
is formed on the GaAs barrier layer
104
. The gate electrode
105
comes into Schottky-contact with the GaAs barrier layer
104
.
Also, a source region
106
and a drain region
107
as high impurity concentration regions are formed in the GaAs barrier layer
104
on both sides of the gate electrode
105
. A source electrode
108
and a drain electrode
109
are formed on the source region
106
and the drain region
107
to come into ohmic-contact with them respectively.
It is normal to grow InGaAs constituting the channel layer
103
without change in the conditions. An indium (In) composition ratio is constant along the layer thickness direction, as shown in FIG.
1
B. Various improvements are applied to the MESFET having such InGaAs channel layer. For example, the MESFET having the structure in which the impurity doped InGaAs channel layer is sandwiched between graded InGaAs layers, or the structure that has the InGaAs channel layer having the thickness smaller than the critical thickness is known. Where the graded InGaAs layer means that the In composition ratio is changed in the layer thickness direction.
In this manner, the MESFET having the structure, in which the InGaAs channel layer is sandwiched between the graded InGaAs layers, is set forth in Patent Application Publication (KOKAI) Hei 9-321061, Patent Application Publication (KOKAI) Hei 4-326734, and Patent Application Publication (KOKAI) Hei 4-251941, for example. In Patent Application Publication (KOKAI) Hei 4-251941, the planar doping is applied to the InGaAs channel layer.
Also, the MESFET having the structure, which has the InGaAs channel layer having the thickness smaller than the critical thickness, is set forth in Patent Application Publication (KOKAI) Sho 63-272080, and Patent Application Publication (KOKOKU) Hei 6-71011, for example.
By the way, when a relationship between a gate voltage and a mutual conductance of the MESFET having the above structure in the prior art is examined, the MESFET exhibits such a characteristic that, as shown in
FIG. 2
, the mutual conductance (g
m
) is changed very steeply as a function of gate voltage (V
g
). Accordingly, the mutual conductance (g
m
) is ready to change due to the fluctuation of the gate voltage or the reduction in the gate voltage and thus the FET characteristic becomes worse.
In addition, if the GaAs barrier layer
104
shown in
FIG. 1A
is undoped, a source resistance is increased and the maximum mutual conductance (g
mmax
) is not increased.
Since the mutual conductance has an influence on the gain and the maximum oscillation frequency of the MESFET, normally the larger one is preferable.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a compound semiconductor device having the MESFET that raises the maximum mutual conductance and changes the mutual conductance as a function of the gate voltage gently, not to sacrifice the transistor characteristics.
According to the present invention, the ternary or quaternary compound semiconductor layer, in which the inside of the energy band gap is smaller than the edge of that by setting the peak of the mixed-crystal ratio of one constituent element in the inside of the layer, is employed as constituent element of the channel layer into which the impurity is doped.
According to this, the peak of the carrier density distribution is set to position into the inside not the surface of the channel layer. Therefore, even if the fluctuation of the gate voltage, the reduction of the gate voltage, etc. is caused, the steep increase/decrease of the carrier density in the channel layer is suppressed and also the mutual conductance that is higher and more stable than the prior art is obtained. The carrier density distribution is changed by adjusting not only the mixed-crystal ratio of the constituent element in the channel layer but also the dosage distribution of the impurity in the channel layer.
Also, since the mixed-crystal ratio distribution of the above element contained in the graded channel layer is gradually and continuously changed like the parabolic profile, for example, crystal distortion is relaxed and thus the high electron mobility is assured in the channel layer. Also, the carrier density to get the sufficient current amount is assured. In addition, since the impurity is doped into the channel layer, the increase of the source resistance is suppressed and also the maximum value of the mutual conductance is increased higher.
Also, the peak of the carrier density distribution in the channel layer is shifted toward the substrate side from the center of the thickness of the channel layer. Therefore, the distance between the depletion layer generated in the barrier layer on the channel layer and the peak of the carrier density distribution is optimized to improve the breakdown voltage characteristic under the gate electrode.
REFERENCES:
patent: 5206527 (1993-04-01), Kuwata
patent: 5321278 (1994-06-01), Nakagawa
patent: 5331410 (1994-07-01), Kuwata
patent: 5349201 (1994-09-01), Stanchina et al.
patent: 5350936 (1994-09-01), Ikalainen et al.
patent: 5371387 (1994-12-01), Ando
patent: 5373168 (1994-12-01), Ando et al.
patent: 5412230 (1995-05-01), Nakagawa
patent: 5477066 (1995-12-01), Nakanishi
patent: 5652440 (1997-07-01), Chang
patent: 5719415 (1998-02-01), Yagura et al.
patent: 5773853 (1998-06-01), Saito
patent: 5780879 (1998-07-01), Unozawa
patent: 5837565 (1998-11-01), Kuroda et al.
patent: 5903018 (1999-05-01), Shimawaki
patent: 63-272080 (1988-11-01), None
patent: 64-2371 (1989-01-01), None
patent: 64-074764 (1989-03-01), None
patent: 4-162539 (1992-06-01), None
patent: 4-251941 (1992-09-01), None
patent: 4-326734 (1992-11-01), None
patent: 5-121453 (1993-05-01), None
patent: 9-321061 (1997-12-01), None
Office Action from Japanese Patent Office mailed Dec. 17, 2002 in Application No. 2000-219108, translation and prior art information list containing explanation of relevance of cited references, (partical).
Fujitsu Quantum Devices Limited
Lewis Monica
Wilczewsid Mary
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