Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Reexamination Certificate
1997-05-30
2001-01-30
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
C257S194000
Reexamination Certificate
active
06180968
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a compound semiconductor device and a method of manufacturing the same and, more particularly, to a field effect transistor having a multilevel recess structure and a method of manufacturing the same.
2. Description of the Prior Art
When an LDD structure is to be realized with an HJFET in order to attain a higher gate breakdown voltage, a lower source resistance, and suppression of the short channel effect and the surface effect, a multilevel recess structure must be formed by performing recess etching in two stages upon two alignment processes in a conventional case. In Japanese Unexamined Patent Publication No. 4-137737, a multilayered mask is used to selectively side-etch the mask, thereby realizing a two-level recess structure with improved controllability in the lateral direction.
When a two-level recess is formed using two alignment processes, misalignment disadvantageously occurs, and the distance between the gate and the n
+
region is difficult to control and shorten. Even if the controllability in the lateral direction is improved using a multilayered mask, as disclosed in Japanese Unexamined Patent Publication No. 4-137737, etching also progresses along the lateral direction in recess etching, and a short gate and control of the recess width cannot be attained.
As for the direction of depth in recess etching, the recess depths at the first and second levels are controlled in terms of time, resulting in poor reproducibility, low controllability, and low uniformity.
SUMMARY OF THE INVENTION
The present invention has been made in consideration of the above situation in the prior art, and has as its object to provide a compound semiconductor device which can be manufactured while precisely controlling the recess width and depth.
To achieve the above object, according to the basic aspect of the present invention, there is provided a compound semiconductor device comprising a semiconductor multilayered structure,
wherein the semiconductor multilayered structure consists of a first recess etching stopper formed on a conductive layer of a compound semiconductor, a first semiconductor layer formed on the first recess etching stopper layer, a second recess etching stopper layer formed on the first semiconductor layer, and a second semiconductor layer formed on the second recess etching stopper layer.
According to the present invention, the first and second semiconductor layers defined in the basic aspect may consist of a compound semiconductor selected from the group consisting of GaAs, InAs, Al
x
Ga
1-x
As (0≦x<1), Al
y
In
1-y
As (0≦y<1), InP, GaP, and compounds thereof.
According to the present invention, the first and second etching stopper layers defined in the basic aspect may consist of a material selected from the group consisting of AlAs, Al
z
Ga
1-z
As (0<z≦1) having an Al composition higher than that of Al
x
Ga
1-x
As, and Al
w
In
1 w
As (0<w≦1) having an Al composition higher than that of Al
y
In
1-y
As.
Further, according to the present invention, the semiconductor multilayered structure defined in the basic aspect has a gate parallel to a [
011
] direction.
To achieve the above object, according to another basic aspect of the present invention, there is provided a method of manufacturing a compound semiconductor device with a semiconductor multilayered structure, comprising the mask formation step, the patterning step, the first anisotropic etching step, and the second anisotropic etching step,
wherein the semiconductor multilayered structure has a first recess etching stopper layer formed on a conductive layer of a compound semiconductor, a first semiconductor layer formed on the first recess etching stopper layer, a second recess etching stopper layer formed on the first semiconductor layer, and a second semiconductor layer formed on the second recess etching stopper layer,
the mask formation step is the process of forming first and second mask layers having different etching rates on the semiconductor multilayered structure,
the patterning step is the process of patterning the second mask layer and patterning the first mask layer using the patterned second mask,
the first anisotropic etching step is the process of anisotropically etching the second semiconductor layer to the second recess etching stopper by using the first and second mask layers, and
the second anisotropic etching step is the process of removing the second recess etching stopper layer at an opening portion, selectively increasing an opening width of the first mask layer by side etching, and then anisotropically etching the second and first semiconductor layers to the second and first recess etching stopper layers, respectively.
The first and second semiconductor layers defined in the basic aspect of the manufacturing method are anisotropically etched by using, as an etching solution, a solution mixture of an aqueous citric acid solution and a hydrogen peroxide solution.
As is apparent from the above aspects, in the present invention, first and second mask layers having different etching rates are formed on a semiconductor multilayered structure. The second mask layer is patterned, and the first mask layer is patterned using the patterned second mask layer. The second semiconductor layer is anisotropically etched to the second recess etching stopper layer by using the first and second mask layers.
In anisotropic etching to the second recess etching stopper layer, a solution mixture of an aqueous citric acid solution and a hydrogen peroxide solution is used as an etching solution. The citric acid-based etching solution can selectively etch a semiconductor layer formed of, e.g., GaAs and a stopper layer formed of, e.g., AlAs, and its etching rate for a (
111
) B plane can be suppressed very small. If this citric acid-based etching solution is used for etching the semiconductor multilayered structure, etching can be stopped at the (
111
) B plane without any side etching in the lateral direction and at the second recess etching stopper layer in the direction of depth.
By using the above-described etching method, the depth and opening width at the first level are determined by the position of the second recess etching stopper layer and the opening dimension of the second mask layer almost independently of the etching time.
Since the opening shape is rate-determined by the (
111
) B plane by forming the gate parallel to the [
011
] direction, the opening at the second level can be made smaller than the opening dimension of the second mask layer.
The second recess etching stopper layer is removed at the opening portion. After the opening width of the first mask layer is selectively increased by side etching, the second and first semiconductor layers are anisotropically etched again to the second and first recess etching stopper layers with a citric acid-based etching solution.
Since the second semiconductor layer is etched only at the opening portion due to the presence of the second recess etching stopper layer, a two-level recess structure can be easily formed. The opening width at the second level is already determined by the initial recess width at the first level. By forming the gate parallel to the [
011
] direction, the opening width decreased upon recess etching at the first level is further decreased upon etching at the second level.
The carrier density of the first semiconductor layer is set lower than that of the second semiconductor layer. The gate electrode is short-circuited with the first semiconductor layer, and is spaced apart from the heavily doped second semiconductor layer. With this arrangement, a high drain breakdown voltage can be attained while surface influences such as a gate lag are avoided. This structure can be easily fabricated in self-alignment. The recess width at the second level in the lateral direction is determined by the initial mask opening width and the thicknesses of the first and second semiconductor layers. The etc
Kasahara Kensuke
Ohkubo Satoru
Ohno Yasuo
Crane Sara
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
LandOfFree
Compound semiconductor device and method of manufacturing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Compound semiconductor device and method of manufacturing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Compound semiconductor device and method of manufacturing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2465792