Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2001-09-05
2002-10-29
Clark, Jasmine J B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S774000, C257S723000, C257S691000
Reexamination Certificate
active
06472738
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a compound semiconductor device and, more particularly, a compound semiconductor device such as a microwave monolithic integrated circuit (MMIC), etc., the characteristics of which are largely affected by a restriction of distance.
2. Description of the Prior Art
In the communication field in recent years, the applications in the higher frequency band among the limited frequency resources are positively developed. As the semiconductor device corresponding to such applications, the MMIC using the compound semiconductor such as GaAs, etc., is employed. The MMIC is designed to overcome the restriction of distance between the elements driven with the high frequency signal by forming a plurality of elements on one substrate. As the elements constituting circuits of the MMIC, there are active elements such as HEMT, MESFET, etc., and passive elements such as a resistor, an inductor, and a capacitor, etc. These elements are connected via wirings.
The MMIC in the prior art has the structure shown in
FIG. 1
, for example. Also, a circuit diagram in the MMIC shown in
FIG. 1
is shown in FIG.
2
.
In
FIG. 1
, a first FET
101
and a second FET
102
are formed at a distance on a compound semiconductor substrate
100
. A gate of the first FET
101
is connected to a first pad
105
via a first wiring
103
and a first capacitor
104
and also is connected a second pad
107
via a second wiring
106
. The second wiring
106
has such a shape that a second capacitor
109
is connected between the second wiring
106
and a first through hole
108
.
A source of the first FET
101
is connected to a second through hole
110
. Also, a drain of the first FET
101
is connected to a gate of the second FET
102
via a third wiring
111
and a third capacitor
112
. Also, a drain of the first FET
101
is connected to a third through hole
116
via a fourth wiring
113
, a first resistor
114
, and a fourth capacitor
115
and also connected to a third pad
118
via a fifth wiring
117
. The fifth wiring
117
is connected to a fourth through hole
120
via a fifth capacitor
119
.
A gate of the second FET
102
is connected to a fourth pad
122
via a sixth wiring
121
. The sixth wiring
121
is also connected to a fifth through hole
124
via a sixth capacitor
123
. A source of the second FET
102
is connected to a sixth through hole
136
. A drain of the second FET
102
is connected to a fifth pad
127
via a seventh wiring
125
and a seventh capacitor
126
. The drain of the second FET
102
is connected to a sixth pad
129
via an eighth wiring
128
and also connected to a seventh through hole
133
via a ninth wiring
130
, a second resistor
131
, and an eighth capacitor
132
. The eighth wiring
128
is also connected to an eighth through hole
135
via a ninth capacitor
134
.
In this case, the above first to eighth through holes are connected to a ground electrode (not shown) on a back surface of the compound semiconductor substrate
100
.
As described above, the MMIC shown in
FIG. 1
has such a structure that the active elements, the passive elements, the wirings, etc., are arranged on one surface of the compound semiconductor substrate and then the elements are connected to each other by wirings that are formed of a conductor such as the metal, etc. Thus, such an effect can be achieved that variation in the distance between the elements can be suppressed.
However, in the MMIC shown in
FIG. 1
, because the gold wire is needed in order to connect the first pad
105
and the fifth pad
127
to external peripheral circuits, the characteristic of the MMIC deteriorates by variation in the wire length.
In addition, if a design for attaining the higher performance to meet the higher frequency is attempted, such design is restricted by the arrangement of the elements. In other words, if connection lengths between respective elements become longer, a resistance component and an inductance component are increased. As a result, a new structure to meet the higher frequency demands is needed.
Based on this fact, it is desired that the connection distances between respective elements should be shortened.
In Patent Application Publication (KOKAI) Hei 8-18004, in order to shorten the connection distances between the elements, a first HEMT and a second HEMT are formed on two crystal active layers formed on both faces of an intermediate insulating layer, respectively, and the first HEMT and the second HEMT are connected through a high-concentration n-type layer buried in the holes that are formed in the crystal active layers and the intermediate insulating layer.
Also, in Patent Application Publication (KOKAI) Hei 8-181211, an SOI (Silicon-On-Insulator) substrate having a silicon oxide layer and a silicon layer is used, and an active element covered with a protection film is formed on the silicon layer, and a passive element is formed on the silicon oxide layer. A first via hole is formed in the protection film, and a second via hole connected to the first via hole is formed in the silicon oxide layer and the silicon layer. A first conductive film connected to the electrodes on the protection film is formed in the first via hole, and a second conductive film connected to the first conductive film is formed in the second via hole. The first conductive film and the second conductive film connect electrodes on the protection film to the passive elements.
In addition, in Patent Application Publication (KOKAI) Sho 58-218130 and Patent Application Publication (KOKAI) Hei 11-214448, integrated circuits are separately formed on upper and lower surfaces of a semiconductor substrate, respectively. However, there is no disclosure that these integrated circuits are connected mutually in the silicon substrate.
By the way, according to the compound semiconductor device set forth in Patent Application Publication (KOKAI) Hei 8-18004, it is difficult to connect respective active elements on both surfaces of the semiconductor substrate to the external circuits under the same conditions. Also, in case the semiconductor substrate is fitted onto the ceramic substrate, the upper active elements and the external circuits are connected via the wires. Therefore, the unevenness of the inductance component and the resistance component caused by the wire connection is inevitable.
Also, in the semiconductor device made of silicon set forth in Patent Application Publication (KOKAI) Hei 8-181211, it is normal that the external circuits are connected to the conductive pads exposed from the protection insulating film that covers the active elements. Thus, the gold wires and the bumps are employed to connect the pads and the external circuits. As a result, the variation in the inductance component accompanied by the connection of the signal system is caused in the semiconductor device.
In addition, in the semiconductor devices set forth in Patent Application Publication (KOKAI) Sho 58-218130 and Patent Application Publication (KOKAI) Hei 11-214448, mutually independent integrated circuits are formed merely on both surfaces of the semiconductor substrate. As a result, because the wire connection to the signal system of either the integrated circuit on the first surface side or the integrated circuit on the second surface side, there exists a variation in the inductance component and the resistance component accompanied by the wire connection.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a compound semiconductor device capable of reducing the restriction on the arrangement of elements constituting the integrated circuit and also suppressing the variation in an inductance component in the high frequency transmission system.
According to the present invention, the active elements are formed on a first surface of the semiconductor substrate, and the signal connection of the active elements is accomplished only by the terminals formed on a second surface of the semiconductor substrate.
Because the active element con
Armstrong Westerman & Hattori, LLP
Clark Jasmine J B
Fujitsu Quantum Devices Limited
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