Active solid-state devices (e.g. – transistors – solid-state diode – Transmission line lead
Reexamination Certificate
1998-11-25
2002-02-12
Quach, T. N. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Transmission line lead
C257S787000, C257S788000
Reexamination Certificate
active
06346741
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a chemical mechanical polishing (CMP) method and composition having applicability to the manufacture of ferroelectric random access memory capacitors, in which a stop layer is employed over the capacitor recess dielectric material to achieve the required planarization of the microelectronic device structure. It is also applicable to the fabrication of other integrated circuit structures, such as capacitor, resistor and inductor structures, which in utilizing multilayer geometries benefit from the inherently planarizing character of CMP.
2. Description of the Related Art
There is currently a major effort in semiconductor companies, worldwide, to commercialize high dielectric constant and ferroelectric thin films in advanced DRAMs and ferroelectric random access memories (FeRAMs), respectively. These material s include BaSrTiO
3
(BST) for DRAMs and PbZrTiO
3
(PZT) and SrBi
2
Ta
2
O
9
(SBT) for FeRAMs.
It is well known that these materials require electrodes made from noble metals or noble metal alloys such as Pt, Ir, IrO
2
, Pt—Ru, etc., and sub-micron patterning of both the noble metals and the ferroelectric films is very difficult because of the absence of volatile products for the elemental constituents. State-of-the-art dry etching processes for Pt and Ir are known to have fundamental difficulties due to the predominantly physical (not chemical) mechanism for material removal, resulting in formation of unwanted structures (sometimes called “ears”) at the edges of the electrodes.
Besides the difficulties in patterning sub-micron capacitors of this type, for high memory density it is also important to fabricate the capacitors directly over a conductive plug to contact transistors in order to reduce the area of the memory cell. This geometry (capacitor over plug) is also known as a stack capacitor configuration. For the conventionally employed materials, e.g., polysilicon or tungsten for the plug, a barrier layer is needed to prevent oxidation of the plug and diffusion of the plug material (p-Si or W) through the noble metal bottom electrode. To overcome such problems, it is desirable to use geometric means to protect the plug/barrier/electrode interfaces from exposure to oxidation.
At present, physical vapor deposition methods and stack capacitor configurations are predominantly used for the fabrication of DRAM and FeRAM microelectronic device structures.
An alternative to the stack capacitor is a trench capacitor, which utilizes an enhanced surface area capacitor on the walls of a trench that is etched directly into doped silicon. In such trench capacitors, the bottom electrode contact is not to a conductive plug (p-Si or W) but to the conductive substrate itself, though the requirements for the barrier are similar to the stack configuration. In trench capacitor architecture, the memory cell's transistors are formed on the surface of wafer adjacent to the top of the trench capacitor.
Ferroelectric capacitors planarized using chemical mechanical polishing are also more versatile for monolithic integration of ferroelectric memory or dynamic random access memory (DRAM) with logic IC (“embedded memory”). The 4-6 levels of metal needed for logic ICs place additional demands on the planarity of the underlying structures. Surface flatness is required in high resolution microlithography in order to stay within the aligner's specified depth of focus.
A variety of semiconductor integrated circuits utilize passive (and in some cases active) filtering techniques that use resistors, capacitors, inductors. There is an accelerating trend toward the incorporation of multiple circuit functions in a single IC, whereas in the past different IC's were fabricated and connected externally on a circuit board, or by another packaging scheme.
Given the economic and performance advantages of monolithic integration of these functions, it is highly desirable to fabricate compact RLC elements directly on the chip during fabrication of the other parts of the IC. It is essential to minimize the number of processing steps as much as possible, and to achieve the highest possible yield for IC devices that are manufactured.
By way of background to the ensuing description of the present invention, a description is set out below of machines used in conventional CMP process operations, polishing pads and slurry compositions used in chemical mechanical polishing.
Three types of mechanical, rotating actions are typically employed in conventional CMP machines. One such type has a rotating wafer carrier. Another revolves the abrasive pad. A third type spins both the wafer carrier and the abrasive pad simultaneously. The polishing pad is pre-soaked and re-wet continuously with a slurry consisting of various particles suspended in a solution. The polishing particles range in size from 10 to 1000 nanometers. The suspension solution generally comprises a diluted base or acid for polishing oxide and metals, respectively. Upon completion of the planarization, the wafers go through a post-CMP clean process in which the residual slurry, ground oxide/metal particles, and other potential contaminants are removed. Most IC manufacturers use a combination of de-ionized (DI) water rinses and nitrogen air drying to accomplish the post-CMP decontamination.
The two most common uses of CMP are oxide and metal (tungsten) plug planarization. The two most essential components of the CMP process are the slurry and the polishing pad.
The polishing pad, generally a polyurethane-based material, performs two primary functions. The polymeric foam cell walls of the pad aid in removal of the reaction products at the wafer surface and the pores within the pad assist in supplying the slurry to the pad/wafer interface.
Progressively more research efforts have focused on further understanding empirical results of the intimate contact between the pad and the pre-planarization surface. Several peculiarities were originally noticed in the material removal rate (RR) as a function of time, pressure and velocity. Many CMP users noticed that the RR decreased tremendously as high throughput processes were attempted. Research showed that deformation of the pad resulted from the brittle, hard surfaces of the ICs structure. The asperity of the pads, or surface roughness due to the type of material, the density of the “pockets,” and abrasive characteristics, was found to decline due to pad layer removal. To alleviate this problem, called “glazing,” the pad was conditioned after an experimentally determined amount of time, or wafer runs. The conditioner was composed of a base material (metal), a diamond grit (for cutting), and a grit-bonding material (ni plating). The plating bonded the diamond grit to the base material. The conditioner then effectively removed the top layer of the pad until excess, non-desired particles were removed and the nominal surface characteristics of the pad were restored. Although this approach allowed the same pads to be used for an extended period of time, it also resulted in other complications.
Specifically, the physical bonding of the diamonds and base material ruptured relatively easily during the conditioning process. New methods of bonding as well as enhanced post-conditioning cleaning were pursued. When the diamonds were chemically bonded to the base material, the additional strength made grit detachment less prominent. The new bonding method allowed a factor of ten more wafers to be polished with the same conditioning pads as compared to the number that were able to be polished with the physically grit-bonded pads.
Pad conditioning plays a larger role in planarization of oxide than in planarization of metals since metals tend to have a higher degree of hardness relative to the pad material.
To aid in transporting the slurry to the pad/wafer interface, new pad structures have been designed. Karaki-Doy and other developers have designed polishing pads with continuous grooves in concentric ellipses across the entire pad. Thi
Bilodeau Steven M.
Russell Michael W.
Van Buskirk Peter C.
Hultquist Steven J.
McLauchlan Robert A.
Quach T. N.
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