Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2001-11-30
2004-05-25
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S959000
Reexamination Certificate
active
06740589
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a chemical-mechanical polishing composition used for a production process for semiconductor devices. More particularly, the invention relates to a chemical-mechanical polishing composition which is preferably applicable to a method for polishing a composite material of a plurality of metallic species, more specifically a composite material including copper and a tantalum compound, in which the removal rate of copper desirably differs from that of the tantalum compound. The present invention also relates to a semiconductor wiring wafer produced through polishing by use of the polishing composition and to a method for producing the wafer.
BACKGROUND OF THE INVENTION
Chemical-mechanical polishing is generally considered to be an effective technique for attaining a finishing surface of high accuracy. In the field of semiconductor device manufacture, progress in integration and layer multiplication of semiconductor devices have called for solutions to a variety of requirements related to planarization, led by the issue of focal depth in photolithography. To this end, chemical-mechanical polishing has been proposed and studied.
As disclosed in, for example, Japanese Patent Publication (kokoku) No. 6-103681 and Japanese Patent Application Laid-Open (kokai) Nos. 6-13287 and 7-233485, as one mode of the chemical-mechanical polishing technique, the Damascene method is a method in which a metallic wiring material is charged into holes or trenches formed on an insulating film provided on a semiconductor wafer, and the wiring material provided above the surface of the insulating film is removed through polishing, thereby forming wiring. This method has been developed for forming wiring of copper, which has low electrical resistance and thought to be suitable as a metallic material for forming fine wiring.
Copper diffuses through the contact surface between a copper layer and an insulating film formed from, for example, silica, into the insulating film. Therefore, when the Damascene method using copper is carried out, a thin diffusion barrier layer is formed on the surface of the insulating film in order to prevent diffusion of copper into the insulating film after trenches are formed on an insulating film, and a copper layer is formed on the barrier layer. Thereafter, the copper layer and the diffusion barrier layer formed above the surface of the insulating film are removed through polishing, to form copper wiring. The diffusion barrier layer is formed from a tantalum compound such as tantalum or tantalum nitride.
In a typical chemical-mechanical polishing method, a semiconductor wafer is pressed at a certain load against a polishing pad affixed to a rotatable table, and while a polishing slurry is fed between the polishing pad and the semiconductor wafer, the table and the wafer are rotated, thereby performing polishing. A typical polishing slurry contains a solution which is chemically active to a substance to be polished, and abrasive exerting mechanical polishing effect are suspended in the solution.
In order to improve production efficiency of semiconductor devices, high removal rates of copper and a metal constituting a diffusion barrier layer are desired. However, since the hardness of the metal used in the diffusion barrier layer is higher than that of copper, difficulty is encountered in removing the metal through polishing at a high rate suitable for removing copper. When the rate of removing copper differs from that of removing the metal used in the diffusion barrier layer, a so-called dishing phenomenon occurs, in which the surface of copper that fills trenches walled by the diffusion barrier layer is depressed, inviting, for example, an increase in wiring resistance and occurrence of short circuit of wiring of upper layers, and resulting in lowering of reliability of the semiconductor device. In addition, in a region where wiring is densely provided, since the width of an insulating film or the diffusion barrier layer surrounded by wiring is narrow, the film or the layer is polished, and wiring trenches are made shallow; i.e., an erosion phenomenon arises.
Usually, a two-step polishing method is performed for polishing such a wiring layer. For example, in a first polishing step, copper is removed at a high rate, and in a second polishing step, copper, a metal used in a diffusion barrier layer, and silica are removed through polishing at substantially the same rate to form a wiring structure.
In the case of the aforementioned polishing method in which copper, the diffusion barrier layer, and an insulating film are polished at substantially the same rate in the second polishing step, a wiring structure of uniform thickness fails to be formed through polishing in the second step when the surface polished in the first step is not planar. Therefore, in the first polishing step, polishing must be stopped at the surface of the diffusion barrier layer without polishing of the metal therein to form a planar surface.
In chemical-mechanical polishing, selectivity in removal rate (i.e., ability to polish with material specificity), is generally attained by suitably selecting a chemically active component to be incorporated in a polishing slurry in chemical-mechanical polishing for forming copper wiring, a method for regulating the ratio of the removal rate of copper to that of a metal used in a diffusion barrier layer is disclosed, for example, in Japanese Patent Application Laid-Open (kokai) No. 2000-160141. JP 2000-160141 discloses a polishing composition containing &agr;-alanine, which provides a high ratio of the removal rate of a copper film to that of a tantalum-containing compound.
As described above, in order to prevent polishing of a diffusion barrier layer and to prevent the erosion phenomenon in the first polishing step for forming copper wiring, the ratio of the removal rate of copper to that of a metal used in the diffusion barrier layer must be large, and the removal rate of the metal used in the diffusion barrier layer must be sufficiently low.
From this viewpoint, polishing of the metal used in the diffusion barrier layer at a suppressed level, which is attained by the conventional technique, is insufficient. Specifically, as described in the Examples of Japanese Patent Application Laid-Open (kokai) No. 2000-160141, the removal rate of a tantalum-containing compound becomes high in accordance with an increase in the removal rate of copper, and maintaining the removal rate of tantalum at a low level such that the erosion phenomenon can be sufficiently prevented is difficult.
In the aforementioned first polishing step, the removal rate of the insulating film must also be low. Since the thickness of a copper layer is not necessarily uniform throughout a semiconductor wafer, when copper provided on the diffusion barrier layer is removed throughout the semiconductor wafer, the copper is removed in an early stage at a region where the thickness of the copper layer is small. As a result, the diffusion barrier layer is polished for a long period of time. Therefore, even when the removal rate of the metal used in the diffusion barrier layer is reduced, the diffusion barrier layer may be removed through polishing, resulting in exposure of the insulating film. However, even in this case, erosion can be prevented by regulating the removal rate of the insulating film.
Japanese Patent Application Laid-Open (kokai) No. 10-279928 discloses potassium hydrogenphthalate serving as a compound for regulating the removal rate of an insulating film. However, the regulation effect is not sufficient for preventing erosion of the insulating film in a wiring portion of high package-density, and the effect of the compound on the removal rate of copper or a metal used in a diffusion barrier layer is not disclosed in this publication.
Japanese Patent Application Laid-Open (kokai) Nos. 2000-160138 and 2000-160140 disclose a polishing composition which attains a high removal rate of a metal and a low removal rate of an insulating film. According t
Sato Hajime
Shimazu Yoshitomo
Dang Phuc T.
Showa Denko Kabushiki Kaisha
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