Cleaning compositions for solid surfaces – auxiliary compositions – Cleaning compositions or processes of preparing – For cleaning a specific substrate or removing a specific...
Reexamination Certificate
2000-12-20
2003-10-07
Webb, Gregory E. (Department: 1751)
Cleaning compositions for solid surfaces, auxiliary compositions
Cleaning compositions or processes of preparing
For cleaning a specific substrate or removing a specific...
C252S079400, C438S693000
Reexamination Certificate
active
06630433
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates to chemical mechanical processes for the planarization of surfaces, and to chemical compositions especially suited thereto. More particularly, this invention relates to compositions for the chemical mechanical planarization of conductive, barrier and dielectric surfaces as typically encountered in the fabrication of integrated circuits, including compositions specifically formulated for chemical mechanical planarization and non-contact chemical planarization of Cu/Ta/TaN.
2. Description of Related Art
Fabrication of integrated circuits (“ICs”) to improve performance and reduce costs involves complex analysis of materials properties, processing technology and IC design. IC's consist of multiple layers of conducting, insulating and semiconductor materials, interconnected in various ways by conducting metallic channels and plugs (“vias”), including various dopants implanted into various materials for producing the electronic functionality desired of the IC. The near-universal trend in the manufacture of integrated circuits is to increase the density of components fabricated onto a given area of wafer, increase the performance and reliability of the ICs, and to manufacture the ICs at lower cost with less waste and fewer defective products generated by the manufacturing process. These goals lead to more stringent geometric and dimensional requirements in the manufacturing process. In particular, etching precise patterns into a layer is facilitated by the layer having a surface as nearly planar as feasible at the start of the patterning process. For the common case of patterning by means of photolithography, a planar surface permits more precise location and dimensioning for focusing the incident radiation onto the surface to be etched than would be possible with a surface having deviations from planarity. Similar conclusions typically apply for electron beam or other means of etching. That is, deviations from planarity of the surface to be etched reduce the ability of the surface to support precisely positioned and precisely dimensioned etches. In the following description of the present invention we focus on the typical etching, planarization and photolithography processes as practiced in the manufacture of ICs. However, this is by way of illustration and not limitation, as those skilled in the art of etching will appreciate that the techniques of the present invention for producing planar surfaces will have applicability in increasing the precision of etching by means other than photolithography. In addition, the present invention is not limited to the field of IC manufacture and may find applicability in other areas of technology requiring planar surfaces.
Chemical Mechanical Planarization (“CMP”) has been successfully integrated into integrated circuit multilayer manufacturing processes to achieve highly planar surfaces as described in text books (for example, “Microchip Fabrication” by Peter Van Zant, 3rd Ed., 1997 and “Chemical Mechanical Planarization of Microelectronic Materials” by J. H. Steigerwald, S. P. Murarka and R. J. Gutman, 1997) and generally known in the art. We note that “CMP” is also used in the art to denote “Chemical Mechanical Polishing” as well as “Chemical Mechanical Planarization”. We use CMP herein synonymously in either sense without distinction.
A typical CMP process is depicted schematically in FIG.
1
. During a CMP process, the wafer,
1
, is typically held inside a rotating carrier and pressed onto a rotating pad,
2
, under pressure,
6
, while an abrasive slurry,
5
, (typically containing particles of abrasive such as SiO
2
, Al
2
O
3
, and the like) flows between the wafer and the pad. The slurry,
5
, will typically contain reagents for chemically etching the wafer,
1
, leading to chemical as well as mechanical removal of material. Thus, in the typical practice of CMP, material removal is effected by a combination of chemical attack and mechanical abrasion.
Typically, the wafer,
1
, will be caused to rotate as depicted by
3
in
FIG. 1
, while the polishing pad will itself rotate (
4
in FIG.
1
).
FIG. 1
depicts the polishing pad and wafer rotating in the same direction (for example, clockwise when viewed from above as in FIG.
1
). However, this is merely for purposes of illustration and counter-rotation of wafer and polishing pad is also practiced. In addition to the rotation of the wafer depicted by
3
in
FIG. 1
, the wafer,
1
, may be caused to oscillate in the plane of the surface being polished, substantially perpendicular to the direction of the applied force,
6
(This oscillatory motion is not depicted in FIG.
1
).
Recent work has indicated the ability to planarize surfaces by purely chemical means, without the need for a polishing pad or mechanical contact with the surface undergoing planarization (Ser. No. 09/356,487, incorporated herein by reference). As described in the referenced application, appropriate etchant chemicals are applied to a spinning wafer under conditions and in such a fashion as to planarize the wafer surface. The techniques described in Ser. No. 09/356,487 are collectively denoted as “spin etch planarization” or SEP. Chemical compositions presented in the present application may be employed in SEP processes for the planarization of Cu/Ta/TaN surfaces as well as in more conventional CMP.
Increasing the speed and performance of ICs typically calls for increasing the density of components on the wafer and increasing the speed at which the IC performs its desired functions. Increasing component density typically requires decreasing the size of conducting channels and vias (or plugs). It is well known that decreasing the cross-section of a current-carrying conductor increases the electrical resistance of the conductor for the same material. Thus, decreasing component size on ICs increases electrical resistance, degrading performance and perhaps leading to unacceptable heating. This is one reason IC developers have been looking for conducting materials for use in IC fabrication having lower electrical resistance. Present IC technology typically makes use of tungsten (chemical symbol W) and aluminum (Al) as conductors. Both have adequate electrical conductivities in present devices, but future generations of IC devices will preferably make use of yet higher conductivity materials. Copper (Cu) is among the leading candidates.
Increasing the density of IC components on the wafer also increases the capacitance of the circuits. That is, bringing charge-carrying circuit elements closer together increases the capacitive coupling between such circuit elements. Higher capacitance is detrimental to circuit performance, especially for higher frequency operation as would typically be encountered in telecommunication applications and elsewhere. However, capacitive coupling between proximate circuit elements can be reduced by reducing the dielectric constant of the insulator or insulating material separating the coupled circuit elements. Thus, in addition to seeking conductors with higher conductivities, insulators with lower dielectric constant (“low k”) are also being sought for use as insulating layers in ICs.
Current multi-layer IC fabrication typically makes use of tungsten (W) CMP processes at each successive circuit level. Typically, blanket films of W, Titanium (Ti) and Titanium Nitride (TiN) are deposited. The films are then typically polished, thereby removing material resulting in (for example) W vias or “plugs” which are inlaid, typically in an SiO
2
dielectric layer. The W plugs act as electrically conducting paths between the metal lines of adjacent layers of the IC. Typically, the metal lines connected by W vias will consists of alloys of Al and Cu in present ICs. In typical present IC designs, Ti and TiN layers are used as barrier layers (to hinder unwanted diffusive intermixing of components during fabrication) and adhesion layers (to promote good bonding between otherwise poorly bound layers and to avoid delamination). Such barri
Levert Joseph A.
Mukherjee Shyama P.
Towery Daniel L.
Zhang Fan
Honeywell International , Inc.
Riordan & McKinzie
Thompson Sandra P.
Webb Gregory E.
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