Composite tantalum capped inlaid copper with reduced...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration

Reexamination Certificate

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C257S704000, C257S761000

Reexamination Certificate

active

07071564

ABSTRACT:
The electromigration and stress migration of Cu interconnects is significantly reduced by forming a composite capping layer comprising a layer of β-Ta on the upper surface of the inlaid Cu, a layer of tantalum nitride on the β-Ta layer and a layer of α-Ta on the tantalum nitride layer. Embodiments include forming a recess in an upper surface of Cu inlaid in a dielectric layer, depositing a layer of β-Ta at a thickness of 25 Å to 40 Å, depositing a layer of tantalum nitride at a thickness of 20 Å to 100 Å and then depositing a layer of α-Ta at a thickness of 200 Å to 500 Å. Embodiments further include forming an overlying dielectric layer, forming an opening therein, e.g., a via opening or a dual damascene opening, lining the opening with α-Ta, and filling the opening with Cu in electrical contact with the underlying inlaid Cu.

REFERENCES:
patent: 6096648 (2000-08-01), Lopatin et al.
patent: 6100184 (2000-08-01), Zhao et al.
patent: 6114243 (2000-09-01), Gupta et al.
patent: 6207552 (2001-03-01), Wang et al.
patent: 6221757 (2001-04-01), Schmidbauer et al.
patent: 6346745 (2002-02-01), Nogami et al.
patent: 6706625 (2004-03-01), Sudijono et al.
patent: 2004/0131878 (2004-07-01), Seet et al.
E. T. Ogawa, et al., “Stress-Induced Voiding Under Vias Connected to Wide Cu Metal Leads”, Apr. 2002, p. 312-321.
D. Edelstein, et al., “A High Performance Liner for Copper Damascene Interconnects”, Watson Research Center, IEEE 2001, p. 9-11.
D. Edelstein, et al., “An Optical Liner for Copper Damascene Interconnectes”, Conference Proceedings ULSI XVII, 2002, p. 541-547.

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