1986-02-12
1987-12-01
Edlow, Martin H.
357 28, 357 55, 357 56, 357 82, 357 88, H01L 2712, H01L 2906, H01L 2504
Patent
active
047107944
ABSTRACT:
Disclosed is a composite semiconductor device, comprising a composite substrate consisting of first and second semiconductor substrates, one surface of each of which is mirror-polished, so that the mirror-polished surfaces are bonded together. The first semiconductor substrate has a space adjacent to the bonding interface, and an annular groove which communicates with the space from a surface of the first semiconductor substrate opposite the bonding interface, the annular groove being formed in a portion of the first semiconductor substrate corresponding to a peripheral edge portion of the space thereof, at least one pillar projecting through the space to the bonding interface from a surface, which is exposed to the space, of a first portion of the first semiconductor substrate which is defined by the space and the annular groove, a first insulating layer, formed in the annular groove, for electrically isolating the first portion from a second portion of the first semiconductor substrate adjacent thereto, a second insulating layer, formed on the pillar or a bonding interface between the pillar and the second semiconductor substrate, for electrically isolating the first portion from the second semiconductor substrate, a first functional element formed in the first portion, and a second functional element formed in the second portion.
REFERENCES:
patent: 3412296 (1968-11-01), Grebene
patent: 4411060 (1983-10-01), Cho
patent: 4467521 (1984-08-01), Spooner et al.
patent: 4638552 (1987-01-01), Shimbo et al.
patent: 4661832 (1987-04-01), Lechaton et al.
Mutter, "Selective Filling of Isolation Trenches in Silicon," IBM Technical Disclosure Bulletin, vol. 25, No. 11B, pp. 6114-6115, 4/83.
Akiyama Tatsuo
Baba Yoshiro
Koshino Yutaka
Edlow Martin H.
Featherstone D.
Kabushiki Kaisha Toshiba
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