Composite semiconductor circuit and method of manufacture

Details Composite semiconductor circuit and method of manufacture Composite semiconductor circuit and method of manufacture

1975-11-17

1977-07-12

Wojciechowicz, Edward J.

357 65, 357 71, 357 80, 357 81, H01L 2348, H01L 3902, H01L 2302

Patent

active

040358305

ABSTRACT:
A process of forming a composite semiconductor integrated circuit by forming one or more epitaxial layers of semiconductor material on a semiconductor substrate, forming pedestals by etching partially through said epitaxial layers to form regions projecting from said substrate and etching through said epitaxial layers to form stress relieving channels in the substrate surrounding the pedestals. A thick layer of easily removable material such as an evaporated layer of chromium plus gold and a plated layer of gold is deposited of sufficient thickness to provide good mechanical support, and the substrate is removed by lapping, grinding or etching until at least the stress relieving channels are exposed thereby forming separate semiconductor elements containing said epitaxial regions. An electrical contact layer is deposited across the surface of the remaining substrate and connected to a thermally conductive support which may be either conductive, such as a block of copper, or insulating, such as a block of beryllium oxide, the support material surrounding the epitaxial regions and completing the construction of the device by forming ohmic and/or rectifying contacts to one or more layers of said epitaxial regions.

REFERENCES:
patent: 3825353 (1974-07-01), Loro
patent: 3893229 (1975-07-01), Aird
patent: 3909929 (1975-10-01), Debesis

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